JPH0227793A - Hybrid integrated circuit - Google Patents
Hybrid integrated circuitInfo
- Publication number
- JPH0227793A JPH0227793A JP17741288A JP17741288A JPH0227793A JP H0227793 A JPH0227793 A JP H0227793A JP 17741288 A JP17741288 A JP 17741288A JP 17741288 A JP17741288 A JP 17741288A JP H0227793 A JPH0227793 A JP H0227793A
- Authority
- JP
- Japan
- Prior art keywords
- conductor layer
- insulating substrate
- board
- integrated circuit
- hybrid integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004020 conductor Substances 0.000 claims abstract description 34
- 239000000758 substrate Substances 0.000 claims description 18
- 229910000679 solder Inorganic materials 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 239000002184 metal Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
Landscapes
- Parts Printed On Printed Circuit Boards (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は混成集積回路に関し、特に装置の薄型化、小型
化を提供する混成集積回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a hybrid integrated circuit, and particularly to a hybrid integrated circuit that allows devices to be made thinner and smaller.
従来この種の混成集積回路は、絶縁基板の表（おもて）
面あるいは裏面に形成された導体層パターンによりイン
ダクタンスを構成していたか（第３図（ａ））、あるい
はフィル等のディスクリート部品によりインダクタンス
を構成していた（第３図（ｂ））。Conventionally, this type of hybrid integrated circuit was manufactured using the front side of an insulating substrate.
The inductance was constructed by a conductor layer pattern formed on the front or back surface (FIG. 3(a)), or by a discrete component such as a fill (FIG. 3(b)).
上述した従来の混成集積回路は、インダクタンスをパタ
ーンで形成する場合、必要なインダクタンスを得るため
にパターン面積を広くとる必要があり、装置の小型化又
は高集積化を図るうえで不都合を生じるという欠点があ
る。The above-mentioned conventional hybrid integrated circuit has the disadvantage that when the inductance is formed by a pattern, the pattern area must be wide in order to obtain the necessary inductance, which is inconvenient when trying to miniaturize or increase the integration of the device. There is.
また、コイル等のディスクリート部品でインダクタンス
を構成した場合は、使用するディスクリート部品の厚さ
により装置の厚さあるいは高さが制限され装置の薄型化
に不都合を生じるという欠点がある。Furthermore, when the inductance is constructed from discrete components such as coils, there is a drawback that the thickness or height of the device is limited by the thickness of the discrete components used, making it difficult to make the device thinner.
本発明の混成集積回路は、絶縁基板とこの絶縁基板の表
（おもて）面に形成された第１の導体層と、絶縁基板の
裏面に形成された第２の導体層を絶縁基板に形成された
スルーホール（貫通穴）とスルーホール内壁あるいは内
部に形成された第３の導体層を有し、第３の導体層は第
１の導体層と、第２の導体層を電気的に導通させており
、第１の導体層、第２の導体層及び第３の導体層により
インダクタンス回路を構成している。The hybrid integrated circuit of the present invention includes an insulating substrate, a first conductive layer formed on the front surface of the insulating substrate, and a second conductive layer formed on the back surface of the insulating substrate. It has a through hole formed and a third conductive layer formed on the inner wall or inside of the through hole, and the third conductive layer electrically connects the first conductive layer and the second conductive layer. The first conductor layer, the second conductor layer, and the third conductor layer constitute an inductance circuit.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例の図であり、第１図（ａ）は
絶縁基板の表（おもて）パターン図、第１図すは絶縁基
板の裏パターン図、第１図Ｃは絶縁基板の縦断面図（Ａ
−Ａ’ ）である。FIG. 1 is a diagram of one embodiment of the present invention, FIG. 1(a) is a front pattern diagram of an insulating substrate, FIG. 1 is a back pattern diagram of an insulating substrate, and FIG. is a vertical cross-sectional view of the insulating substrate (A
-A').
厚さ０．６３５ａｍ＋のアルミナセラミックの絶縁基板
１の表（おもて）面にＭｌの導体層２が厚膜印刷で厚さ
１２μｍ程度で形成され絶縁基板１の裏面には第２の導
体層３が厚さ１２μｍ程度で形成さ九、絶縁基板１に直
径０．３ｍｍ程度のスルーホール４が形成されており、
第１の導体層２と第２の導体層３はスルーホール４の内
壁に形成された第３の導体層５により電気的に導通して
いた。第１の導体層２．第２の導体層３．第３の導体層
５によりインダクタンス回路を形成している。A conductive layer 2 of Ml is formed on the front surface of an insulating substrate 1 made of alumina ceramic with a thickness of 0.635 am+ to a thickness of about 12 μm by thick film printing, and a second conductive layer is formed on the back surface of the insulating substrate 1. 3 is formed with a thickness of about 12 μm, and a through hole 4 with a diameter of about 0.3 mm is formed in the insulating substrate 1.
The first conductor layer 2 and the second conductor layer 3 were electrically connected to each other by a third conductor layer 5 formed on the inner wall of the through hole 4 . First conductor layer 2. Second conductor layer 3. The third conductor layer 5 forms an inductance circuit.
第２図は本発明の他の実施例の縦断面図で放熱板付混成
集積回路の例を示す。一実施例と同様に絶縁基板ｌに第
１の導体層２．第２の導体層３゜スルーホール４及び第
３の導体層５が形成されており第１の導体層２．第２の
導体層３．第３の導体層５によりインダクタンスを構成
している。絶縁基板ｌの裏面には第４の導体層６が厚さ
１２μｍ程度で形成され、厚さ２．５−程度の銅製の金
属部材７と、第４の導体層６が半田等のソルダー８によ
りろう付けされている。さらに、第２の導体層３及び第
３の導体層５が金属部材７及び第４の導体層６と電気的
導通がない様にセラミック等の絶縁層９が厚さ３０μｍ
程度で形成されている。FIG. 2 is a longitudinal sectional view of another embodiment of the present invention, showing an example of a hybrid integrated circuit with a heat sink. As in the first embodiment, a first conductor layer 2 is formed on an insulating substrate l. A second conductor layer 3. A through hole 4 and a third conductor layer 5 are formed in the first conductor layer 2. Second conductor layer 3. The third conductor layer 5 constitutes an inductance. A fourth conductor layer 6 with a thickness of about 12 μm is formed on the back surface of the insulating substrate l, and a copper metal member 7 with a thickness of about 2.5 μm and the fourth conductor layer 6 are formed with a solder 8 such as solder. It is brazed. Further, an insulating layer 9 made of ceramic or the like has a thickness of 30 μm so that the second conductor layer 3 and the third conductor layer 5 are not electrically conductive with the metal member 7 and the fourth conductor layer 6.
It is formed to a certain extent.
以上説明したように本発明は絶縁基板の表裏両面の導体
パターンとスルーホールによりインダクタンス回路を構
成することンこよう、第３図（ａ）に示す様な絶縁基板
の表又は裏面の片側の木によってインダクタンスを形成
していた従来例に比べてインダクタンス回路の基板占有
面積を約１／２に減らすことができる。又、第３図（ｂ
）に示す様なコイル等のディスクリート部材１０を絶縁
基板１に半田等のソルダー８でろう付けして使用した従
来例に比べて導体印刷のみで形成した本発明は装置の薄
型化を提供できる。さらに装置の製造においてディスク
リート部材を回路にろう付する工数の削減と部材の資材
費の削減効果が見込まれる。As explained above, the present invention allows an inductance circuit to be constructed using conductor patterns and through holes on both the front and back surfaces of an insulating substrate. The area occupied by the inductance circuit on the substrate can be reduced to about 1/2 compared to the conventional example in which an inductance is formed. Also, Figure 3 (b
) The present invention, which is formed only by conductive printing, can provide a thinner device compared to the conventional example in which a discrete member 10 such as a coil is brazed to an insulating substrate 1 with a solder 8 such as solder. Furthermore, it is expected to reduce the number of man-hours required to braze discrete components to circuits in device manufacturing, as well as reduce material costs.
第１図（ａ）は本発明の一実施例の表パターンを示す平
面図、第１図（ｂ）は本発明の一実施例の裏面パターン
を示す平面図、第１図（ｃ）は第１図（ａ）、第１図（
ｂ）のＡ−Ａ’線断面図、第２図は本発明の他の実施例
の縦断面図、第３図（ａ）、第３図（ｂ）は従来例の縦
断面図である。
１、・・・・・・絶縁基板、２・・・・・・第１の導体
層、３・・・・・・第２の導体層、４・・・・・・スル
ーホール、５・・・・・・第３の導体層、６・・・・・
・第４の導体層、７・・・・・・金属部材、８・・・・
・・ソルダー ９・・・・・・絶縁層、１０・・・・・
・ディスクリート部材（コイル等）。
代理人 弁理士 内 原 音
量ｌ凹（Ｃ）
６手４６キ停層
翳２ 図FIG. 1(a) is a plan view showing a front pattern of an embodiment of the present invention, FIG. 1(b) is a plan view showing a back pattern of an embodiment of the present invention, and FIG. Figure 1 (a), Figure 1 (
FIG. 2 is a longitudinal sectional view of another embodiment of the present invention, and FIGS. 3(a) and 3(b) are longitudinal sectional views of a conventional example. DESCRIPTION OF SYMBOLS 1...Insulated substrate, 2...First conductor layer, 3...Second conductor layer, 4...Through hole, 5... ...Third conductor layer, 6...
- Fourth conductor layer, 7... Metal member, 8...
...Solder 9...Insulating layer, 10...
・Discrete components (coils, etc.). Agent Patent Attorney Hara Uchi Volume 1 (C) 6 hands 46 stops layer 2 Diagram
Claims (1)
記絶縁基板に形成されたスルーホールで電気的導通をと
ることにより形成されているインダクタンスを有するこ
とを特徴とする混成集積回路A hybrid integrated circuit characterized by having an inductance formed by electrically connecting conductor layers formed on one principal surface and the other principal surface of an insulating substrate through through holes formed in the insulating substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17741288A JPH0227793A (en) | 1988-07-15 | 1988-07-15 | Hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17741288A JPH0227793A (en) | 1988-07-15 | 1988-07-15 | Hybrid integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0227793A true JPH0227793A (en) | 1990-01-30 |
Family
ID=16030475
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17741288A Pending JPH0227793A (en) | 1988-07-15 | 1988-07-15 | Hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0227793A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04116886A (en) * | 1990-09-06 | 1992-04-17 | Toko Inc | Power composite component |
-
1988
- 1988-07-15 JP JP17741288A patent/JPH0227793A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04116886A (en) * | 1990-09-06 | 1992-04-17 | Toko Inc | Power composite component |
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