JPH02280249A - Cache memory controller - Google Patents

Abstract

PURPOSE:To improve an access speed to data except for an instruction code by providing a cache enable deciding circuit. CONSTITUTION:When a code/data identifying signal 2 from a processor 13 is the date except for the instruction code, the following actions are executed. First, in the case of a miss, when a valid bit 4 is meaningful, a cache enable deciding circuit 12 makes a cache enable signal 9 meaningless, the processor 13 directly accesses a main memory 15, and the data are not loaded to a cache memory 14. On the other hand, when the valid bit 4 is meaningless, the cache enable deciding circuit 12 makes the cache enable signal 9 meaningful, the data from the main memory 15 are loaded to the cache memory 14, and simultaneously, they are returned to the processor 13. Thus, the access speed to the data except for the instruction code can be improved.

Description

[Detailed description of the invention]

r Industrial Application Field J This invention relates to a cache memory control device used in a computer system, etc., and particularly to improving the hit rate thereof.

[Conventional technology]

Generally, in order to prevent delays in the operation of a high-speed processor, a cache memory, which is a small-capacity, high-speed local buffer, is sometimes provided in addition to the low-speed main memory. Cache memory stores frequently used data or last used data in main memory, and when the processor accesses memory, if the necessary data is in this cache memory, it saves time. Access to such main memory is no longer necessary, improving system performance. Figure 2 shows known documents showing this relationship, such as "Nikkei Electronics J & 3869204-207 (198
6-1-13, published by Nikkei McGraw-Hill, Inc.), and FIG. 3 is a block diagram of the structure of a conventional cache memory dedicated to direct mudded instructions. 2 and 3, a processor (13) provides an address signal (1) to a cache memory (14) and a main memory (15), while a code/data identification signal (2) is provided to a cache memory (14). send. These responses are transmitted from the cache memory (14) or main memory (15) to the processor (13) as data signals (10). Here, as shown in detail in FIG. 3, the cache memory (14) includes a tag memory (3), a valid bit (4) indicating that the data in the cache memory is valid, and a data memory (5). , a tag comparator (6), a data multiplexer (7) that selects the data requested by the processor (13), and a data buffer (11) that mediates the data signal (10) between the processor (13) and the cache memory (14). ) and other functional parts. In such a configuration, during a read cycle of the processor (13), the address signals (1) from Am to AI++ become the input addresses of the tag memory (3) and data memory (5), and the tag comparator (6) Based on the output of (3), the valid bit (4), and An to ^-+1 of the address signal (1), it is determined whether there is a hit or not, and a hit/miss signal is output. Address signal (1)
input addresses Am to Al+1 are stored in the memory, and when a hit occurs, the data requested by the processor (13) is selected by the data multiplexer (7) by the output from the data memory (5), and the data is The signal is sent back to the processor (13) as a data signal (10) via a buffer (11). On the other hand, if you make a mistake, take the main note! Data corresponding to the input address is transferred from J (15) to the data memory (5) via the data buffer (11), and is transferred to the tag memory (3).
) is updated, and the processor (13)
The requested data is returned to . Here, since the cache memory (14) is dedicated to instructions, if the code/data identification signal (2) from the processor (13) is data other than the instruction code, the cache enable signal (9) becomes invalid. No cache operation is performed, and the processor (13) and main memory (15)
) will be accessed directly. [Problem to be Solved by the Invention J] Conventional cache memory control devices have the above-mentioned structure, so when an instruction-only cache is used to improve the hit rate for instruction fetch operations, it is difficult to store information other than instruction codes. This invention has been made with the object of solving this problem, and has a cache 1a for data other than instruction codes. An object of the present invention is to obtain a cache memory control device that can perform cache operations. [Means for Solving the Problems J] A cache memory control device according to the present invention provides a
The cache enable determination circuit receives three inputs: a miss signal, a valid bit, and a processor code/data identification signal, and determines whether or not to perform a cache operation. [Operation J] Even if the data requested by the processor is data other than an instruction code, the cache/enable determination circuit according to the present invention loads the requested data into the cache if invalid data is stored in the cache memory. , hereafter,
Since caching is performed in the same way as for code, access speed for data other than instructions is improved. If the command requested by the processor is an instruction code, the hit rate will be equivalent to that of an instruction-only cache. Embodiment J of the Invention An embodiment of the invention will be described below with reference to FIG. In the figure, the same parts as in FIGS. 2 and 3 are designated by the same reference numerals. As shown in FIG. 1, a cache enable determination circuit (12) is provided in the present invention. This cache enable determination circuit (12) inputs the code/data identification signal (2) issued by the processor (13), the valid bit (4) and code pit (11) of the cache memory, and generates a cache enable signal ( 9) is output. In the cache memory control device having such a configuration, in the read cycle of the processor (13), the code/data identification signal (2) from the processor (13) is
If it is an instruction code, it operates in the same way as a conventional instruction-only cache. However, if the code/data identification signal (2) from the processor (13) is data other than an instruction code, the following operation is performed. First, if the valid bit (4) is significant in the case of a miss, the cache enable determination circuit (12) makes the cache enable signal (9) invalid and the processor (1)
3) directly accesses the main memory (15) and no data is loaded into the cache memory (14). On the other hand, if the valid bit (4) is invalid, the cache enable determination circuit (12) makes the cache enable signal (9) significant, and the data from the main memory (15) is loaded into the cache memory (14) and the processor It is returned to (13). Next, when data other than the instruction code is hit, the data signal (10) is output from the data memory (5) via the data multiplexer (7) and the data buffer (11), as in the case of the instruction code, and the hit cycle is is completed. As described above, according to the present invention, when the requested data from the processor (13) is an instruction code, a high-speed cache operation is performed as in the conventional method, and when the requested data is other than an instruction code, the cache operation is also performed, so that the overall The hit rate is improved and the access speed to data other than instruction codes is improved. In the above embodiments, a direct mated type cache memory has been described, but it goes without saying that other types of cache memory, such as a fully associative cache and a set arithmetic cache, can also be used. [Effect of the Invention J] As explained above, this invention has a structure in which a cache enable determination circuit is provided, so that if the data stored in the cache memory at the time of a miss is invalid, the data requested by the processor is changed to an instruction code. The configuration is configured such that requested data is loaded into the cache regardless of whether or not the instruction code is present, and the access speed for data other than instruction codes is improved compared to the case where a conventional instruction-only cache is used.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a cache memory control device according to an embodiment of the present invention, FIG. 2 is a block diagram of a memory system using an instruction cache, and FIG. 3 is a block diagram of a conventional instruction-only cache memory control device. It is a diagram. In the figure, (1) is an address signal, (2) is a code/
data identification signal, (3) is tag memo'), (4) is valid bit, (5) is data memory, (7) is data multiplexer, (8) is hit/miss signal, (9) is cache enable signal, (12) is a cache enable determination circuit, (13) is a processor, (14) is a cache memory, and (15) is a main memory. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] In a cache memory control device that sends corresponding data in a cache memory to a processor according to an instruction from a processor, and loads the corresponding data from a main memory to a cache memory when the corresponding data does not exist in the cache memory, the cache memory Valid bits and hit/miss signals in the cache memory as well as signals from the processor are input, and if the data requested by the processor is data other than the instruction code and the data at the corresponding address in the cache memory is invalid. The present invention further includes a cache enable determination circuit which enables a load operation of the cache memory and disables the load operation to the cache memory when data at a corresponding address in the cache memory is valid and a miss occurs. Characteristic cache memory control device