JPH0253152A - Cache memory controller - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a cache memory control device used in a computer system, etc., and particularly to improving the hit rate thereof.

[Prior Art] Generally, in order to prevent delays in the operation of a high-speed processor, a cache memory, which is a small-capacity, high-speed local buffer, is sometimes provided in addition to a low-speed main memory. Cache memory stores frequently used data or last used data in main memory, and when the processor accesses memory, if the necessary data is in this cache memory, it saves time. Such access to main memory is no longer necessary, improving system performance.

Figure 2 shows a well-known document showing this relationship, such as "Nikkei Electronics J No. 386 p204-207 (1
986-1-11, published by Nikkei McGraw-Hill, Inc.), and FIG. 3 is a block diagram of the structure of a conventional cache memory exclusively for direct Matsubuto instructions.

2 and 3, a processor (13) provides an address signal (1) to a cache memory (14) and a main memory (15), while a code/data identification signal (2) is provided to a cache memory (14). send. These responses are transmitted from the cache memory (14) or main memory (15) to the processor (13) as data signals (10). Here, as shown in detail in FIG. 3, the cache memory (14) includes a tag memory (3), a valid pit (4) indicating that the data in the cache memory is valid, and a data memory (5). , a tag comparator (6), and a data multiplexer (7) for selecting data requested by the processor (13).

In such a configuration, during a read cycle of the processor (13), the address signal (1) changes from A- to A, e+i.
becomes the input address of the tag memory (3) and data memory (5), and the tag comparator (6) receives the output of the tag memory (3), the valid pit (4), and the address signal (
From An to Ai+1 in 1), it is determined whether there is a hit or not, and a hit/miss signal is output. AJul is stored in the memory from the input address AI of the address signal (1), and if it is hit, the data memory (5)
Based on the output from the data multiplexer (7), data requested by the processor (13) is selected and the signal is sent back to the processor (13) as a data signal (10).

On the other hand, if there is a miss, the data corresponding to the input address is transferred from the main memory (15) to the data memory (5), and as a result, the contents stored in the tag memory (3) are updated, which causes the valid pit (4) to be transferred. emits a significant signal, so the processor (1
3) The requested data is returned.

Here, since the cache memory (14) is dedicated to instructions, if the code/data identification signal (2) from the processor (13) is data other than the instruction code, the cache enable signal (9) becomes invalid. No cache operation is performed, and the processor (13) uses the main memory (15
) will be accessed directly.

[Problems to be Solved by the Invention] Conventional cache memory control devices have the above-mentioned configuration, so when an instruction-only cache is used to improve the hit rate for instruction fetch operations, it is difficult to store information other than instruction codes. There was a problem in that the data could not be cached.

The present invention was made with the aim of solving these problems, and is a cache memory that has a hit rate for instruction fetch operations equivalent to that of an instruction-only cache, and that can also perform caching operations for data other than instruction codes. The purpose is to obtain a control device.

[Means for Solving the Problems] A cache memory control device according to the present invention includes a code bit that is added to a cache memory to indicate that data stored in the memory is an instruction code, and this code bit. and a cache enable determination circuit that inputs valid pits and the dominant code/data identification signal of the processor and determines whether or not to perform a cache operation.

[Operation] Even if the data requested by the processor is data other than the instruction code, the cache enable determination circuit according to the present invention does not perform the cache operation if invalid data or data other than the instruction code is stored in the cache memory. This improves the access speed for data other than instruction commands.

If the command requested by the processor is an instruction code, the hit rate will be equivalent to that of an instruction-only cache.

[Example] An example of the present invention will be described below based on FIG. 1. In the figure, the same parts as in FIGS. 2 and 3 are designated by the same reference numerals.

As shown in FIG. 1, in this invention, a data memory (5)
A code bit (11) is attached to the tag memory (3) to indicate that the data stored therein is an instruction code, and a cache enable determination circuit (12) is attached to the tag memory (3).
) is provided. This cache enable determination circuit (
12) inputs the code/data identification signal (2) issued by the processor (13), the valid pit (4) and code bit (11) of the cache memory, and outputs a cache enable signal (9).

In the cache memory control device having such a configuration, in the read cycle of the processor (13), the code/data identification signal (2) from the processor (13) is
If it is an instruction code, it operates in the same way as a conventional instruction-only cache.

However, if the code/data identification signal (2) from the processor (13) is data other than an instruction code, the following two operations are performed. One of them is that the cache enable determination circuit (12) inputs signals from the valid pit (4) and code bit (11) of the cache memory and determines whether the data stored in the data memory (5) is valid. In this case, the cache enable determination circuit (12) makes the cache enable signal (9) invalid, and the processor (13) directly accesses the main memory (15).

The other case is when the cache enable determination circuit (12) determines that the data stored in the data memory (5) is invalid or data other than the instruction code. The circuit (12) makes the cache enable signal (9) significant, performs a normal cache operation, and returns the data requested by the processor (13) as a data signal (10) through high-speed processing.

As described above, according to the present invention, when the requested data from the processor (13) is an instruction code, a high-speed cache operation is performed as in the conventional method, and when the requested data is other than an instruction code, the cache operation is also performed, so that the overall The hit rate is improved and the access speed to data other than instruction codes is improved.

In the above embodiments, a direct matrix type cache memory has been described, but it goes without saying that other types of cache memory such as a fully associative cache and a set-associative cache can also be used.

[Effects of the Invention] As explained above, this invention has a structure in which a code bit is added to the cache memory and a cache enable determination circuit is provided, so that the data stored in the cache memory is invalid or has a code other than an instruction code. In the case of data, the cache operation is performed regardless of whether the data requested by the processor is an instruction code or not.
This has the effect of improving the access speed for data other than instruction codes.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a cache memory control device according to an embodiment of the present invention, FIG. 2 is a block diagram of a memory system using an instruction cache, and FIG. 3 is a block diagram of a conventional instruction-only cache memory control device. It is a diagram. In the figure, (1) is an address signal, (2) is a code/
Data identification signal, (3) is tag memory, (4) is valid pit, (5) is data memory, (7) is data multiplexer, (9) is cache enable signal, (1
1) is a code bit, (12) is a cache enable determination circuit, (13) is a processor, (14) is a cache memory, and (15) is a main memory. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Agent Patent Attorney Masuo Oiwa (and 2 others) Block diagram of memory system Figure 2 5: Block diagram of cache-memory control device of data memory embodiment Figure 1 Block diagram of conventional cache memory control device 3. Written amendment to figure procedure (voluntary) 5. Subject of amendment February 2, 1999 Detailed explanation of the invention in the specification. 6. Contents of the amendment 3. Person making the amendment

Claims (1)

[Claims] A cache memory control device that sends the relevant data in the cache memory to the processor according to instructions from the processor, and if the relevant data does not exist in the cache memory, loads the relevant data from the main memory to the cache memory and then performs a cache operation. inputting a code bit provided in the cache memory to indicate that the data in the memory is an instruction code, a signal from this code bit and a valid bit in the cache memory, and a signal from the processor; If the data requested by the processor is data other than an instruction code, and the data at the corresponding address in the cache memory is an instruction code, the cache operation is disabled, and if the data at the corresponding address in the cache memory is not an instruction code, the cache operation is disabled. A cache memory control device comprising a cache enable determination circuit that enables cache operation.