JPH0228364A - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor deviceInfo
- Publication number
- JPH0228364A JPH0228364A JP63145153A JP14515388A JPH0228364A JP H0228364 A JPH0228364 A JP H0228364A JP 63145153 A JP63145153 A JP 63145153A JP 14515388 A JP14515388 A JP 14515388A JP H0228364 A JPH0228364 A JP H0228364A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- polysilicon
- oxide film
- forming
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- 238000004519 manufacturing process Methods 0.000 title claims description 4
- 239000012535 impurity Substances 0.000 claims abstract description 19
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 16
- 229920005591 polysilicon Polymers 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims abstract description 4
- 238000009792 diffusion process Methods 0.000 claims description 4
- 230000001590 oxidative effect Effects 0.000 claims 1
- 238000005468 ion implantation Methods 0.000 abstract description 2
- 239000000126 substance Substances 0.000 abstract 1
- 238000001947 vapour-phase growth Methods 0.000 abstract 1
- 238000010438 heat treatment Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 235000012149 noodles Nutrition 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/201—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits
- H10D84/204—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits of combinations of diodes or capacitors or resistors
- H10D84/209—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits of combinations of diodes or capacitors or resistors of only resistors
Landscapes
- Bipolar Transistors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
- Formation Of Insulating Films (AREA)
- Bipolar Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
この発明は半導体基板上に絶縁膜により完全分離して抵
抗を形成する半導体装置の製造方法に関するものである
。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application This invention relates to a method of manufacturing a semiconductor device in which a resistor is formed on a semiconductor substrate completely isolated by an insulating film.
従来の技術
従来、この種の半導体装置は、初めにトランジスタを形
成する工程で、第４図に示すように、半導体基板５内に
エミッタ領域３の作り込みやベース４へのコンタクトの
作り込み時に不純物拡散処理を実施するが、この時窓形
成のための絶縁膜１上にも不純物が拡散され、不純物層
２が形成される。この絶縁股上に第５図に示すように、
ポリシリコンを形成して抵抗６を作り込むが、ポリシリ
コン形成時、またはその後の熱処理により、不純物層２
から不純物がポリシリコン中に拡散され、不純物拡散処
理の温度時間、量及び熱処理の温度１時間、雰囲気によ
ってその拡散による影響は一定ではな（、本来必要とす
る抵抗値の調整を困難にしたり、一定の抵抗値を持続さ
せることができなかった。2. Description of the Related Art Conventionally, this type of semiconductor device has been manufactured in the first step of forming a transistor, as shown in FIG. An impurity diffusion process is performed, and at this time, impurities are also diffused onto the insulating film 1 for forming a window, and an impurity layer 2 is formed. As shown in Figure 5, on this insulation rise,
The resistor 6 is formed by forming polysilicon, but the impurity layer 2 is
Since impurities are diffused into polysilicon, the influence of the diffusion is not constant depending on the temperature and time of the impurity diffusion treatment, the amount of heat treatment, the temperature of the heat treatment for 1 hour, and the atmosphere (this may make it difficult to adjust the resistance value that is originally required). It was not possible to maintain a constant resistance value.
発明が解決しようとする課題
このような従来の構成では、上記のように、本来一定の
範囲内にあるべき抵抗値が、抵抗形成後変化するという
問題があった。本発明はこのような問題点を解決するも
ので、抵抗形成時の抵抗がこの後の熱処理によって変化
することなく、抵抗を内蔵した半導体装置を作ることを
目的とするものである。Problems to be Solved by the Invention In such a conventional configuration, as described above, there is a problem in that the resistance value, which should originally be within a certain range, changes after the resistance is formed. The present invention is intended to solve these problems, and aims to produce a semiconductor device with a built-in resistor without the resistance during resistor formation being changed by subsequent heat treatment.
課題を解決するための手段
この問題点を解決するために本発明は、トランジスタ形
成時のエミッタ領域またはベースコンタクト領域での不
純物拡散された絶縁膜とポリシリコン形成との間に、不
純物が混入されていない絶縁膜をトランジスタの特性に
影響のない温度で低温酸化膜を形成した上にポリシリコ
ン抵抗を形成し、抵抗値の変動を完全になくしたもので
ある。Means for Solving the Problems In order to solve this problem, the present invention provides a method in which impurities are mixed between the polysilicon layer and the impurity-diffused insulating film in the emitter region or base contact region during transistor formation. A polysilicon resistor is formed on a low-temperature oxide film at a temperature that does not affect the characteristics of the transistor, completely eliminating fluctuations in resistance value.
作用
この構成により、完全に絶縁膜上の不純物の影響がな（
なり、安定したポリシリコン抵抗が形成される。Function: This configuration completely eliminates the influence of impurities on the insulating film (
Thus, a stable polysilicon resistor is formed.
実施例
第１図は本発明の実施例で得られた半導体装置の断面図
である。この図を参照して、本発明を詳しくのべる。Embodiment FIG. 1 is a sectional view of a semiconductor device obtained in an embodiment of the present invention. The present invention will be described in detail with reference to this figure.
絶縁膜１をマスクとして、半導体基板５内のベース領域
４に、エミッタ域３がイオン注入によって形成される。Emitter region 3 is formed in base region 4 in semiconductor substrate 5 by ion implantation using insulating film 1 as a mask.
このとき、絶縁膜１の表面にも、不純物層２が形成され
る。そこで、全面に、無添加酸化膜７を、低温での化学
気相成長法によって形成し、その上に、ポリシリコン抵
抗６を設ける。これにより、ポリシリコン抵抗６は無添
加酸化膜７で不紗物層２と分離され、同不純物層２から
、不純物の不測の導入が防止される。At this time, the impurity layer 2 is also formed on the surface of the insulating film 1. Therefore, an additive-free oxide film 7 is formed on the entire surface by chemical vapor deposition at a low temperature, and a polysilicon resistor 6 is provided thereon. Thereby, the polysilicon resistor 6 is separated from the impurity layer 2 by the non-additive oxide film 7, and the accidental introduction of impurities from the impurity layer 2 is prevented.
第２図は、本発明をバイポーラ抵抗内蔵トランジスタ素
子に適用した実施例で得られた半導体装置の断面図、第
３図はその等価回路図である。本素子はベース領域４、
エミッタ領域３ （ＮｐＮタイプの場合）を形成した後
、ノン−ドープド低温酸化膜７を数１０００Ａ形成した
のち、ポリシリコン膜を数１０００Ａ形成し、通常のフ
ォトリソグラフィによって、一定の長さと幅を有する抵
抗６を形成し、アルミニウム電極配線８によってトラン
ジスタのエミッターベース間またはベースに抵抗が挿入
されるようにして、一定の抵抗値をバイアス抵抗として
内蔵させることができた。FIG. 2 is a sectional view of a semiconductor device obtained in an example in which the present invention is applied to a bipolar resistor built-in transistor element, and FIG. 3 is an equivalent circuit diagram thereof. This element has a base region 4,
After forming the emitter region 3 (for NpN type), a non-doped low-temperature oxide film 7 of several thousand amps is formed, a polysilicon film of several 1000 amps is formed, and a certain length and width is formed by normal photolithography. By forming the resistor 6 and inserting the resistor between the emitter and base of the transistor or between the base of the transistor using the aluminum electrode wiring 8, it was possible to incorporate a certain resistance value as a bias resistor.
発明の効果
本発明によれば、絶縁膜上に無添加酸化膜を低温で形成
し、この上にポリシリコン抵抗を形成することにより、
その後の熱過程によっても、下層の絶縁膜から、不純物
が導入されて、ポリシリコン抵抗の抵抗値が変化すると
いう不測の要因が排され、安定な半導体装置が得られる
。Effects of the Invention According to the present invention, by forming an additive-free oxide film on an insulating film at a low temperature and forming a polysilicon resistor on this film,
The subsequent thermal process also eliminates the unexpected factor of introducing impurities from the underlying insulating film and changing the resistance value of the polysilicon resistor, resulting in a stable semiconductor device.
第１図は本発明の実施例により得られた半導体装置の断
面図、第２図は本発明を採用した抵抗内蔵トランジスタ
の断面図、第３図はその等価回路図、第４図、第５図は
従来例装置の製造過程断面図、構造断面図である。
１・・・・・・絶縁膜、２・・・・・・絶縁膜中に拡散
された不純物層、３・・・・・・エミッタ領域、４・・
・・・・ベース領域、５・・・・・・半導体基板、６・
・・・・・ポリシリコン抵抗、７・・・・・・ノンドー
プド低温酸化膜、８・・・・・・電極材料
代理人の氏名 弁理士 中尾敏男 ほか１名第
図
第
図
ノ −−！Ａ麺ヒン（！１
焦添Ｓ蒙化斌FIG. 1 is a sectional view of a semiconductor device obtained according to an embodiment of the present invention, FIG. 2 is a sectional view of a transistor with a built-in resistor adopting the present invention, FIG. 3 is an equivalent circuit diagram thereof, and FIGS. The figures are a sectional view of a manufacturing process and a structural sectional view of a conventional device. DESCRIPTION OF SYMBOLS 1... Insulating film, 2... Impurity layer diffused in the insulating film, 3... Emitter region, 4...
... Base region, 5 ... Semiconductor substrate, 6.
...Polysilicon resistor, 7...Non-doped low-temperature oxide film, 8...Name of electrode material representative Patent attorney Toshio Nakao and one other person Figure Figure No --! A noodle hin (!1 Jiaozoe S Menghuabin
Claims (1)
体の表面に酸化性雰囲気中での不純物拡散処理により低
温酸化膜を形成し、その上にポリシリコン抵抗を形成す
ることを特徴とする半導体装置の製造方法。A method for manufacturing a semiconductor device, comprising: forming a low-temperature oxide film on the surface of a transistor substrate that has been fabricated up to the emitter region by impurity diffusion treatment in an oxidizing atmosphere, and forming a polysilicon resistor thereon. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63145153A JPH0228364A (en) | 1988-06-13 | 1988-06-13 | Manufacturing method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63145153A JPH0228364A (en) | 1988-06-13 | 1988-06-13 | Manufacturing method of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0228364A true JPH0228364A (en) | 1990-01-30 |
Family
ID=15378648
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63145153A Pending JPH0228364A (en) | 1988-06-13 | 1988-06-13 | Manufacturing method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0228364A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101522117B1 (en) * | 2010-10-08 | 2015-05-20 | 다나카 기킨조쿠 고교 가부시키가이샤 | Precious metal paste for bonding semiconductor element |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5132536A (en) * | 1974-09-14 | 1976-03-19 | Mitsui Seiyaku Kogyo Kk | P aminomechiruansokukosan no seizohoho |
| JPS59186358A (en) * | 1983-04-06 | 1984-10-23 | Sanyo Electric Co Ltd | Semiconductor device with built-in resistor |
-
1988
- 1988-06-13 JP JP63145153A patent/JPH0228364A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5132536A (en) * | 1974-09-14 | 1976-03-19 | Mitsui Seiyaku Kogyo Kk | P aminomechiruansokukosan no seizohoho |
| JPS59186358A (en) * | 1983-04-06 | 1984-10-23 | Sanyo Electric Co Ltd | Semiconductor device with built-in resistor |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101522117B1 (en) * | 2010-10-08 | 2015-05-20 | 다나카 기킨조쿠 고교 가부시키가이샤 | Precious metal paste for bonding semiconductor element |
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