JPH0228731A - Micro computer for evaluation - Google Patents

Abstract

PURPOSE:To switch a using area in RAM of evaluation mass production micro computer (MC) in accordance with the RAM capacity of mass production MC by writing data corresponding to the RAM capacity of the MC in the specified address of EPROM. CONSTITUTION:Data corresponding to the RAM capacity of mass production MC is set to one at the time of 256 words, and to zero at the time of 1,128 words. When a write control signal 1 is impressed on EPROM1, a program is written into the designated address of a program counter PC2 and data 1 in the 0-th bits of the specified address 1a. When a clock signal is impressed on the trigger terminal of a latch circuit 9, data 1 of the 0-th bits of the specified address in a data terminal is outputted from an output terminal. Consequently, load address data X3 is impressed on a load address decoder 4 from an AND gate 5. Consequently, the address of RAM3 is designated by data X0-X3 and column address data Y0-Y3, and the program integrated to mass-production MC of the RAM capacity with 246 words is evaluated.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an evaluation microcomputer that evaluates programs installed in a plurality of mass-produced microcomputers having different RAM capacities.

(b) When using a conventional technology evaluation microcomputer to evaluate programs installed in multiple mass-produced microcomputers with different RAM capacities, the area used in the RAM of the evaluation microcomputer is It is necessary to switch according to the RAM capacity. Conventionally, the evaluation microcomputer was equipped with a dip switch, and this dip switch was used to switch the RAM capacity of the evaluation microcomputer.
Furthermore, the RAM capacity of the evaluation microcomputer was switched by wiring the RAM capacity switching terminal without providing a dip switch in the evaluation microcomputer.

(c) Problems to be solved by the invention However, when the evaluation microcomputer is provided with a dip switch, the thickness increases, which reduces the degree of freedom in space when incorporating the evaluation microcomputer into a set. There was a problem. Also RAM
The thickness problem mentioned above can be solved by wiring the capacitance switching terminal, but if the wiring breaks after the evaluation microcomputer is installed in the set, it will be difficult to repair and will reduce the serviceability of the set. There was a problem with this.

(D) Means for Solving the Problems The present invention provides an evaluation microcomputer that evaluates programs incorporated in a plurality of mass-produced microcomputers having different RAM capacities, in which the programs incorporated in the mass-produced microcomputers are written. a nonvolatile memory in which data corresponding to the RAM capacity of the mass-produced microcomputer is written to a specific address;
a RAM having a RAM capacity greater than the RAM capacity of the plurality of mass-produced microcomputers; a clock generation circuit that generates a clock signal by applying a reset signal; A latch circuit that latches data according to the RAM capacity of the computer, and a control circuit that controls the number of bits of address data that specifies the address of the RAM based on the latch data of the latch circuit,
The problem is solved by switching the area used in the RAM according to the RAM capacity of the mass-produced microcomputer.

(E) Function The present invention is effective as described below when provided in an evaluation microcomputer that evaluates programs installed in a plurality of mass-produced microcomputers having different RAM capacities. In other words, the program installed in the mass-produced microcomputer is written into the non-volatile memory, and with data corresponding to the RAM capacity of the mass-produced microcomputer written to a specific address in the non-volatile memory, a reset signal is applied to the clock generation circuit. Then, a clock signal is generated from the clock generation circuit, and when the clock signal is applied to the latch circuit, the RAM of the mass-produced microcomputer is
Data corresponding to the capacitance is latched into the latch circuit. When the latch data of the latch circuit is applied to the control circuit, the number of bits of the address data specifying the address of the RAM of the evaluation microcomputer is controlled by the control circuit. From now on, RA of the evaluation microcomputer
The usable area in M is switched according to the RAM capacity of the mass-produced microcomputer.

(f) Example The details of the present invention will be specifically explained with reference to the illustrated embodiments.

The drawing is a block diagram showing an evaluation microcomputer of the present invention.

In the drawing, (1) is EPROM (non-volatile memory)
By applying a write control signal of "1", a program built into the mass-produced microcomputer is written, and data corresponding to the RAM capacity of the mass-produced microcomputer is written to the specific address (1a). Here, the specific address (1a>
The left side of is the lower bit. (2) is the EPROM
(1) This is a PC (program counter) that specifies the address.

(3) is a RAM, which has a RAM capacity that is greater than the RAM capacity of the mass-produced microcomputer to be evaluated. (4
) is a row address decoder that selects one of a plurality of word lines arranged in a matrix for a plurality of bit lines in the RAM (3), and is a row address decoder that selects 3-bit row address data "X6 X+ X*". is applied directly, and 1-bit row address data "X," is applied via an AND gate (5) as a control circuit. (6) is a column address decoder which selects one of a plurality of bit selection lines in order to select one of the plurality of bit lines, and includes 4-bit column address data ry.

Y + Y * Y 8 J is applied directly. (7)
is a clock generation circuit, which generates a clock signal by applying a reset signal via an inverter (8). (9) is a latch circuit which, upon application of the clock signal, latches data corresponding to the RAM capacity of the mass-produced microcomputer, and this latch data controls the AND gate (5). Furthermore, the 4-bit row address data 'Xo
One of the plurality of word lines is selected based on XIXx XsJ or 3-bit row address data 'XOXI Xx', and 4-bit column address data 'Yo
Y+ YQY8. Since one of the plurality of bit selection lines is selected based on
It is possible to evaluate programs built into mass-produced microcomputers having a RAM capacity of one word. In addition, the data corresponding to the RAM capacity of a mass-produced microcomputer is "1" when the RAM capacity is 256 words, and R
10 when the AM capacity is 128 words.

First, when evaluating a program installed in a mass-produced microcomputer with a RAM capacity of 256 words,
When the write control signal "11" is applied to the EPROM (1) with the data written in the EPROM (1) erased in advance by ultraviolet light, the program installed in the mass-produced microcomputer is transferred to the PC (2). The data "1" corresponding to the RAM capacity of the mass-produced microcomputer is written to the address specified by the PC (
2) is written to the Oth bit of the specific address (1a) specified by. Then, in order to reset the evaluation microcomputer, when a reset signal of 10 is applied to the inverter (8), the
A reset signal of 1'' is applied to the clock generation circuit 7), and a clock signal is generated from the clock generation circuit 7). When this clock signal is applied to the T (rigger) terminal of the latch circuit (9), the data “1” of the 0th bit of the specific address (1a) applied to the D (data) terminal is It is latched at the rising edge of the clock signal and output from the Q (output) terminal at the falling edge of the clock signal. Therefore, AND
Since one input terminal of the gate (5) can be held at "1" by the latch data of the latch circuit (9), the 1-bit row address data "X," is input to the AND gate (5).
) to the row address decoder (4). Therefore, the address of RAM (3) is 4-bit row address data "xDX.

XtXs” and 4-bit column address data “Yo
In other words, the area used in RAM (3) is 2'X2'=25, which is equal to the RAM capacity of a mass-produced microcomputer.
It will be 6 words. From this, EPROM (1
) by running the program written in 2.
A program installed in a mass-produced microcomputer with a RAM capacity of 56 words will be evaluated.

Next, when evaluating a program installed in a mass-produced microcomputer with a RAM capacity of 128 words,
In the above case, the RA of the mass-produced microcomputer
Only the data corresponding to the M capacity needs to be set to 101, and AN
Since one input terminal of the D gate (5) is held at rO'' by the latch data of the latch circuit (9), 1
Always r□ as bit row address data “X3”
is sent to the row address decoder (
4) will be applied. Therefore, the address of RAM (3) is the 3-bit row address data "X.

X, X, and 4-bit column address data'Y
o It will be specified based on YHYx Y3J, that is, the area used in RAM (3) is 23X2' = 1, which is equal to the RAM capacity of the mass-produced microcomputer.
It will be 28 words. From this EPROM (
By executing the program written in 1),
A program installed in a mass-produced microcomputer with a RAM capacity of 128 words will be evaluated.

From the above, in order to evaluate a program installed in a mass-produced microcomputer with a RAM capacity of 256 words or 128 words, it is necessary to
The data “1” or “0” according to the M capacity is stored in the EPROM.
Since it is sufficient to write to the Oth bit of the specific address (1a) in (1), the evaluation microcomputer's RA
The area used in M (3) can be easily switched depending on the RAM capacity of the mass-produced microcomputer, such as 256 words or 128 words. Therefore, all the conventional problems will be solved.

In this embodiment, the RAM capacity of the mass-produced microcomputer is 256 words or 128 words, but the latch circuit (9) and the AND gate (5 ) are similarly provided, and 'x,.

If any of the row address data 'Xo It goes without saying that programs installed in mass-produced microcomputers having RAM capacities other than those mentioned above can be evaluated. Further, an EEPROM may be provided in place of the EPROM (1).

(G) Effects of the Invention According to the present invention, in order to evaluate a program installed in a mass-produced microcomputer with a different RAM capacity, data corresponding to the RAM capacity of the mass-produced microcomputer is written to a specific address of a nonvolatile memory. As a result, the area used in the RAM of the evaluation microcomputer can be easily switched according to the RAM capacity of the mass-produced microcomputer. In addition, even if this evaluation microcomputer is incorporated into Sera 1~, the degree of freedom in space will not be reduced, and since there is no need for wiring to switch the RAM capacity, there are advantages such as improved serviceability on the set side. It will be done.

[Brief explanation of the drawing]

The drawing is a block diagram showing an evaluation microcomputer of the present invention. (1)-EPROM, (la)-specific address,
(3>...RAM, (5)...AND gate, (7)...clock generation circuit, (9)...
latch circuit.

Claims (1)

[Claims] (1) In an evaluation microcomputer that evaluates programs installed in multiple mass-produced microcomputers with different RAM capacities, the program installed in the mass-produced microcomputers is written, and at the same time data is written in accordance with the RAM capacity of the mass-produced microcomputers. a non-volatile memory in which is written to a specific address, and an R larger than the RAM capacity of the plurality of mass-produced microcomputers.
A RAM having an AM capacity, a clock generation circuit that generates a clock signal when a reset signal is applied, and a clock generation circuit that latches data according to the RAM capacity of the mass-produced microcomputer when the clock signal is applied. a latch circuit; and a control circuit that controls the number of bits of address data specifying an address in the RAM according to the latch data of the latch circuit; An evaluation microcomputer characterized by switching according to the