JPH02288681A - Picture memory address correction circuit - Google Patents

Abstract

PURPOSE:To attain one chip configuration for picture-in-picture system by displaying a master.slave picture called as the picture-in-picture with a memory capacity by one field. CONSTITUTION:A master.slave picture discrimination circuit 2 discriminating an even/odd number of a field outputted from the master.slave picture and a field memory write/read line address comparator 3 comparing a write address of a data of a field memory for the slave picture with a readout address of an address data and an address correction circuit 4 outputting a pulse to an OR circuit 6 depending on the result of the output of the both are provided in the subject circuit. Then the picture-in-picture is realized with the memory capacity by one field. Thus, one chip configuration of the picture-in-picture is attained in addition to the low cost by the memory capacity reduction.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an image memory address correction circuit. More specifically, the present invention relates to a circuit that corrects the read address of a child screen image memory that has a function of displaying a parent screen and a child screen called picture-in-picture.

Conventional technology When combining two television screens, one as a main screen and the other as a child screen, so that the child screen is displayed as part of the main screen on one screen, compressed data for the child screen is stored. image memory is used.

The child screen data written in this memory is read out in synchronization with the display of the main screen to realize the picture-in-picture described above.

Current television screens have two types of screens, called even fields and odd fields, which are created by increment scanning, and the scanning line positions on the television screen are different.

Therefore, when combining two screens into a parent and child screen, it is necessary to determine whether the fields of each screen are even/odd and to adjust the display position of the child screen.

Consider a case where the image memory for a child screen is configured with only a capacity for one field. Since the parent screen and the child screen operate asynchronously, the even/odd fields of the parent screen and the child screen do not necessarily match. For example, if the data of the child screen held in the image memory is of an odd field every time the parent screen outputs an even field, the data of the odd field of the child screen will be output to the even field of the parent screen. be done. Subsequently, when the parent screen outputs an odd field, the data of the child screen held in the image memory becomes that of the even field, and the data of the even field of the child screen is output to the odd field of the parent screen. Ru.

This situation is shown in FIGS. 3(a) to 3(d). Figure 3 (a
) to (d) are examples in which one frame of the sub-screen is composed of four scanning lines (two each for odd and even fields). FIG. 3(a) shows small screen data for odd fields, and FIG. 3(b) shows small screen data for even fields.

When the data in FIGS. 3(a) and 3(b) are normally output to the odd and even fields of the parent screen, respectively, the child screen output signal becomes the image signal shown in FIG. 3(C). On the other hand, when the even/odd fields are switched between the parent screen and the child screen as described above, the child screen output signal is the odd field data of the child screen, as shown in the image signal shown in FIG. 3(d). Data reversal occurs between the data and the even field data.

Conventionally, in order to avoid this phenomenon, dedicated image memories were prepared for each of the even and odd fields of the child screen, and the image memory of either one was changed according to the field being scanned by the parent screen. It was reading data.

Problems to be Solved by the Invention As mentioned above, conventionally, a memory for two fields was required to realize a picture-in-picture system. Therefore, a large capacity memory is required, making it difficult to integrate into a single chip, resulting in problems such as increased cost and increased occupied area.

SUMMARY OF THE INVENTION An object of the present invention is to provide an image memory address correction circuit that solves the problems of the prior art described above and that only requires the use of one field's worth of memory.

Means for Solving the Problems According to the present invention, a first television screen is used as a main screen, and a picture-in-picture screen is provided in which a second television screen is displayed as a sub-screen in a part of the main screen. In the circuit that specifies the address in the memory for sub-screen image data used when realizing this, a specification that specifies the read address of the memory where data for one field of the second television screen is compressed and stored in the sub-screen. means for determining whether the field of the first television screen and the field of the second television screen data read from the memory are an even field or an odd field; and an output of the determining means. and an address correction circuit that corrects the read address in address units corresponding to the amount of data displayed on one scanning line of the first television screen when reading data from the memory. A correction circuit is provided.

Operation The image memory address correction circuit of the present invention determines whether the fields of the parent and child screens are odd or even, and
If the even/odd field data of the child screen is reversed from the field of the parent screen, the read address of the child screen memory is corrected to correct the data reversal. Therefore,
By using the circuit of the present invention, it is possible to configure a child screen with a memory capacity for one field.

EXAMPLES Hereinafter, the present invention will be explained in more detail with reference to Examples, but the following disclosure is merely an example of the present invention and does not limit the technical scope of the present invention in any way.

Embodiment FIG. 1 shows a block diagram of an example of an image memory address correction circuit of the present invention. The circuit shown in FIG. 1 includes a parent/child screen field determination circuit 2 that determines whether the fields output by the parent screen and the child screen are even/odd, and a data write address and a data read address of the field memory for the child screen. A field memory write/read line address comparator 3 is provided for comparing the field memory write/read line address comparator 3, and an address correction circuit 4 is provided for outputting a pulse to an OR circuit 6 based on the output results of both. A pulse is also output to the OR circuit 6 from the field memory read line address counter increment pulse generation circuit 1, and the output of the OR circuit 6 is output from the field memory read line address counter 5.
is input. The field memory read line address of the child screen indicated by the address counter 5 is incremented by the pulse output from the OR circuit 6.

The operation of the image memory address correction circuit of the present invention will be described below with reference to FIGS. The image memory address correction circuit of the present invention was used in combination with a sub-screen field memory having a capacity for one field.

FIGS. 2(a) to 2(b) show child screen signals output on the main screen. In FIGS. 2(a) to 2(a), solid lines 11 indicate odd-numbered fields of the parent screen, and broken lines 12 indicate even-numbered fields of the parent screen. Also, ■ to ■ indicate data of child screens output in numerical order, respectively.

FIG. 2(a) shows a case where the data of the child screen is normally output and the even/odd fields of the parent screen and the child screen match. In this case, in the circuit of the present invention, the pulse generating circuit 1 emits a pulse in synchronization with the output of the main screen, and the address counter 5, which indicates the address of the data to be read next from the sub-screen field memory, is sequentially incremented. .

The synchronization between the parent screen and the child screen is out of order, and as shown in Figure 2, etc., the field data of the child screen is
When the odd signal is output in a reversed state, the field determination circuit 2 detects this and outputs a signal to the address correction circuit 4. Address correction circuit 4 outputs a pulse to OR circuit 6, and address counter 5 is incremented. In this embodiment, the child screen data of the odd field that is output to the even field of the main screen is output after address correction. This situation is illustrated in FIGS. 4(a) and 4(b). FIG. 4(a) shows a child screen signal output during the main screen, in which the odd field data and the even field data are reversed. When the address of the odd field data (data in memory) of the sub screen is corrected as shown above, the address is incremented, and the odd field data of ■ and ■ are changed to ■ as shown by the arrows.
, ■ are output above the even field data. Fourth
Figure (b) shows the output data after address correction. Odd field data ■ is not read out when the address is incremented. That is, although the output position is shifted by one line data as a result of address correction, the data of odd and even fields are output in the correct order, and the image becomes normal.

On the other hand, a case will be described in which the reversal of write and read addresses that occurs when compressing child screen data is corrected.

To compress the child screen to 1/n in the vertical direction and 1/m in the horizontal direction with respect to the main screen, write one vertical line of the source signal to the memory for every n lines, and in the horizontal direction, Write 1 for read
/m times the speed.

Therefore, writing to the sub-screen field memory is slow, but reading is fast.
The read address may overtake the write address. If the read address overtakes the write address, the data one field before is output, so address correction is required.

Figure 2 (C) shows that the fields are even/
The figure shows a case where the read address overtakes the write address when the odd numbers match.

When the read address overtakes the write address, the child screen data becomes one field earlier.

Therefore, the even/odd status of the fields of the child screen is reversed from that of the parent screen. In the correction circuit of the present invention, when the read address overtakes the write address, the address comparator 3 detects the overtaking and issues a signal to the address correction circuit 4. The address correction circuit 4 issues a pulse to the OR circuit 6 and increments the address counter 5, as shown in FIG. 2(C).
The field data of ■, ■, and ■ are output above the field data of ■, ■, and ■, respectively.

FIG. 2(d) shows a case where the read address overtakes the write address when the even/odd field of the child screen is reversed from that of the main screen.

Before overtaking occurs, the address of the odd field small screen data is corrected as described above and then output. Therefore, the field data of ■ and ■ in FIG. 2(d) are output above the field data of ■ and ■, respectively.

On the other hand, after overtaking, the address of the child screen data output to the even field of the main screen before overtaking has already been corrected, so the address of the child screen data of the even field that is output to the even field of the main screen after overtaking has also been corrected. Therefore, the addresses of the child screen data of the odd fields that are output to the odd fields of the main screen after overtaking are also corrected.

As described above, the image memory address correction circuit of the present invention has the following features:
To output data from the field memory of the child screen in order even if the even/oddness of the field data of the child screen is reversed from that of the parent screen by using only the child screen field memory with the capacity for one field. make it possible.

As described in detail, by using the image memory address correction circuit of the present invention, it is possible to realize picture-in-picture with a memory capacity for one field. Therefore, it is possible not only to reduce costs simply by reducing the memory capacity, but also to realize a single-chip picture-in-picture system, which has been difficult in the past.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an example of the image memory address correction circuit of the present invention, and FIGS. 2(a) to (6) are diagrams illustrating correction of the output signal of a sub-screen by the circuit of the present invention. 3(a) and 3) are examples of the odd field and even field data of the child screen, respectively, and FIG. (b) is an output screen in which the data is output normally, and an output screen in which the even/odd field is reversed. This is a diagram illustrating how an output screen outputted with even/odd reversed is corrected. [Main reference numbers] 1... Field memory read line address counter increment pulse generation circuit, 2... Parent/child screen field determination circuit, 3... Field memory write/read line address comparator, 4... Address correction circuit, 5... Field memory line address counter, 6... OR circuit,

Claims (2)

[Claims] (1) A child screen image used when realizing picture-in-picture in which the first television screen is the main screen and the second television screen is displayed as a child screen in a part of the main screen. In the circuit for specifying an address in the data memory, a specifying means for specifying a read address of the memory for compressing and storing data for one field of the second television screen in a sub-screen; field and the second read from memory.
determining means for determining whether a field of television screen data is an even field or an odd field; and an output of the determining means, when reading data from the memory, one scan of the first television screen is performed. An image memory address correction circuit comprising: an address correction circuit that corrects read addresses in address units corresponding to the amount of data projected on a line. (2) The image memory address correction circuit includes a comparison means for comparing the address of the second television screen data written in the memory with the address of the second television screen data read from the memory, and the Claim 1, wherein the address correction circuit corrects the read address also based on the output of the comparison means.
).The image memory address correction circuit described in ).