JPS6126869B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a CRT display device, and more particularly, to a CRT display device that displays images stored in an image memory or NTSC standard images individually, or displays both images in a mixed manner. .

Traditionally used in computer systems
A CCRT display device stores predetermined image information calculated by a computer in an image memory, and displays the stored image information as an image by reading it out by sequential scanning synchronized with raster scanning.

However, in recent years, with the spread of personal computers and home computers, it has become possible to display images from a computer individually on the same screen, or to display a mixture of NTSC standard images from a video disk device and images from a computer. There is a need for a device that can perform the following functions in order to make more economical use of display devices and to expand the functionality of computer systems.

However, conventionally used CRT display devices display images using a progressive scanning method, while NTSC standard CRT display devices display images using an interlaced scanning method. Different images cannot be displayed on the same screen.

This invention was made in view of these circumstances, and its purpose is to provide a CRT capable of displaying computer-calculated images or NTSC standard images individually, or displaying both images in combination.
The purpose of the present invention is to provide a display device.

To this end, the CRT display device according to the present invention is provided with a circuit that switches the scanning method to either progressive scanning or interlaced scanning depending on the presence or absence of a video synchronization signal of the NTSC standard.

Hereinafter, the present invention will be explained in detail based on illustrated embodiments.

The figure is a block diagram showing one embodiment of the present invention. In the figure, a detection circuit 1 detects a synchronization signal included in an NTSC video signal VED by comparing a reference voltage corresponding to this synchronization signal with the video signal VED, and when a synchronization signal is detected, outputs a detection signal A of logic "0". This detection signal A is supplied to a horizontal synchronizing signal generation circuit 2 and a vertical counter circuit 3.

The horizontal synchronization signal generation circuit 2 includes a first circuit 20 that generates a horizontal synchronization signal HD ₁ for interlaced scanning according to the NTSC standard, and a horizontal synchronization signal HD ₂ for progressive scanning.
and a second circuit 21 that generates a logic “0”
When the detection signal A of logic "1" is input as a control signal, the switch SW is switched to the first circuit 20 side and the horizontal synchronization signal HD ₁ is selected and output, and when the detection signal A of logic "1" is input, the switch The SW is switched to the second circuit 21 side to selectively output the horizontal synchronizing signal HD ₂ . A horizontal synchronizing signal (HD ₁ or HD ₂ ) selectively output from this circuit 2 is supplied to a vertical counter circuit 3.

When the detection signal A of logic "0" is input, the vertical counter circuit 3 outputs signals YO to Yn for displaying the image information stored in the image memory 4 by interlaced scanning. That is, the detection signal A of logic "0" is inverted by the inverter 30 and supplied to the AND gates 31 and 34. The other input of the AND gate 31 receives a horizontal synchronization signal (HD ₁ or
HD ₂ ) is supplied, and its output is configured to be supplied as a count input signal to a counter 38 via a NOR gate 33. Further, the carry signal CARY of the counter 38 is supplied to the other input of the AND gate 34, and its output is the output of the NOR gate 3.
6 to the clock input (CP) of a D-type flip-flop 37.

Therefore, when the detection signal A of logic "0" is generated, the horizontal synchronization signal HD ₁ for interlaced scanning is input from the horizontal synchronization signal generation circuit 2, so that the counter 38 receives the signal HD 1 every time the signal HD ₁ is generated. increments the count value. In addition, the flip-flop 37 is connected to a counter 38.
The Q output is repeatedly inverted between logic "0" and logic "1" by the carry signal CARY which is generated every time the counting operation of .

The Q output of the flip-flop 37 is output as a signal Y0 of the ^20th least significant bit of the line number signal Y indicating the position of the horizontal scanning line in the vertical direction, and the count output signal of the counter 38 is outputted as the 2nd bit of the 2nd bit of the signal Y. ¹ to most significant bit 2 ⁿ signal Y1
It is configured to be output as ~Yn.

Therefore, when the detection signal A of logic "0" is generated, the signal Y indicates the position of the odd or even horizontal scanning line in accordance with the inversion operation of the flip-flop 37. That is, during the period when the flip-flop 37 is not set, the signal Y indicates the even-numbered horizontal scanning line position, and the counting operation of the counter 38 completes one round (that is, the scanning of the first field is completed), and the flip-flop 37 is set. During the setting period, the signal Y indicates the odd-numbered horizontal scanning line position. Therefore, if image information is stored in the image memory 4 for each horizontal scanning line and the signal Y is supplied as an address signal, only image signals at even addresses are read out during the period when the flip-flop 37 is not set. Then, when the flip-flop 37 is set, only the image signals at odd addresses are sequentially read out.

This makes it possible to read the image information stored in the image memory 4 in synchronization with the NTSC standard synchronization signal. Therefore, this read image information
By superimposing it on the NTSC standard video signal,
It is possible to display a mixture of an NTSC standard image and an image corresponding to the image information stored in the image memory 4.

In this case, when no image information is stored in the image memory 4, only the NTSC standard image can be displayed independently.

On the other hand, when the detection signal A of logic "1" is input, the vertical counter 3 outputs signals Y0 to Yn for displaying the image information by sequentially scanning the image information stored in the image memory 4. That is, the detection signal A of logic "1" is supplied to AND gates 32 and 35. The other input of the AND gate 32 is a signal Y0 from the Q output of the flip-flop 37.
is supplied, and its output is supplied as a count input signal to a counter 38 via a NOR gate 33. The other input of the AND gate 35 is supplied with a horizontal synchronizing signal HD ₂ for sequential scanning, and its output is supplied to the clock input (CP) of a flip-flop 37 via a NOR gate 36.

Therefore, when the detection signal A of logic "1" is generated, the flip-flop 37 outputs the horizontal synchronization signal HD ₂
The reversal operation is repeated every time . i.e. the signal
Y0 repeats logic "0" and "1" every time the horizontal synchronizing signal HD ₂ is generated. On the other hand, the counter 38 receives the signal
Since Y0 is supplied as a count input signal,
The count value is incremented each time signal Y0 occurs. As a result, the signal Y consisting of the signals Y0 to Yn sequentially indicates odd and even horizontal scanning lines every time the horizontal synchronizing signal _HD2 is generated. As a result, the image information stored in the image memory 4 can be read out in synchronization with the signal HD ₂ using a sequential scanning method. That is, the image information stored in the image memory 4 can be displayed at high resolution by sequential scanning.

In the above embodiment, the counter 38 is configured to generate a carry signal when the counting operation completes one cycle, but it may also be configured to generate a borrow signal.

As is clear from the above explanation, according to this invention
CRT display devices are equipped with a circuit that switches the scanning method to either progressive scanning or interlaced scanning depending on the presence or absence of an NTSC standard video synchronization signal, so the image calculated by a computer or the NTSC standard image is It is possible to display both images individually or in combination with both images.
This allows video signals from a video disk device or the like to be coupled to the computer system, which is extremely effective in expanding the functionality of the computer system.

[Brief explanation of the drawing]

The figure is a block diagram showing one embodiment of the present invention. 1...Detection circuit, 2...Horizontal synchronization signal generation circuit, 3...Vertical counter circuit, 4...Image memory.

Claims (1)

[Claims] 1. A detection circuit that detects the presence or absence of a video synchronization signal of the NTSC standard; a detection signal of this detection circuit is used as a control input;
a horizontal synchronization signal generation circuit that selectively outputs a horizontal synchronization signal for interlaced scanning when a TNSC standard video synchronization signal is detected, and a horizontal synchronization signal for sequential scanning when the video synchronization signal is not detected; When a counter circuit that counts the horizontal synchronization signal supplied from the horizontal synchronization signal generation circuit and the detection circuit detect an NTSC standard video synchronization signal, the counter circuit repeatedly inverts the signal using a carry signal or a borrow signal of the counter circuit according to the detection signal. 1. A CRT display device comprising: a vertical counter circuit having a flip-flop that sends out an output; and a read address signal for an image memory being configured by the output signals of the counter circuit and the flip-flop.