JPH0228990A - Semiconductor device mounting method - Google Patents
Semiconductor device mounting methodInfo
- Publication number
- JPH0228990A JPH0228990A JP17811788A JP17811788A JPH0228990A JP H0228990 A JPH0228990 A JP H0228990A JP 17811788 A JP17811788 A JP 17811788A JP 17811788 A JP17811788 A JP 17811788A JP H0228990 A JPH0228990 A JP H0228990A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- lead
- wiring board
- wiring pattern
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3415—Surface mounted components on both sides of the substrate or combined with lead-in-hole components
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
[産業上の利用分野]
本発明は、下面にリードピンをマトリックス状に配列し
たピングリッドアレイと呼ばれる半導体装置の実装方式
に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a semiconductor device mounting method called a pin grid array in which lead pins are arranged in a matrix on the lower surface.
[従来の技術]
近時、電子機器の小型化、薄形化等の要請と、高機能化
、多様化によるI10端子の増大に伴って、半導体装置
は益々多端子化しており、例えば、外径28mm X
28mm、厚さ3.6關の半導体装置において、端子の
数は160本、各端子の幅は300 wn、各端子の間
隔が650−程度のものが使用されている。[Prior Art] In recent years, with the demand for smaller and thinner electronic devices and the increase in the number of I10 terminals due to higher functionality and diversification, semiconductor devices are becoming more and more multi-terminal. Diameter 28mm
In a semiconductor device having a size of 28 mm and a thickness of 3.6 mm, the number of terminals used is 160, the width of each terminal is 300 wn, and the interval between each terminal is about 650 mm.
そして、配線基板への実装時には、これら微細な各端子
を配線基板に設け°た微細な配線パターンにそれぞれ接
続しなければならないので、各端子のx、y、z方向の
位置管理が厳しい精度で要求される。このようなことか
らパッケージの四方に端子を設ける方式の半導体装置に
おいては、端子の数の増大は限界に近づきっ\あるが、
半導体装置の端子数は今後益々増加し、近い将来におい
て400〜600本以上に達するものとみられている。Then, when mounting on a wiring board, each of these minute terminals must be connected to a minute wiring pattern provided on the wiring board, so the position of each terminal in the x, y, and z directions must be controlled with strict precision. required. For this reason, in semiconductor devices in which terminals are provided on all sides of the package, the increase in the number of terminals is approaching its limit.
The number of terminals of semiconductor devices will continue to increase in the future, and is expected to reach 400 to 600 or more in the near future.
このような半導体装置の多端子化に対応するため、最近
では第3図に示すように、半導体装置1の下面にリード
ピン2をマトリックス状に配列したピングリッドアレイ
(PGA)と呼ばれる半導体装置(以下単に半導体装置
という)が実用化されている。In order to cope with the increase in the number of terminals in semiconductor devices, recently, as shown in FIG. (simply referred to as semiconductor devices) have been put into practical use.
この半導体装置は、従来、第4図に示すように配線基板
4の配線パターン6に、リードビン2に対応してそれぞ
れスルーホール5を設け、一部のり−ドビン2に位置決
め用ストッパ3を設けて各リードビン2をスルーホール
5に差込み、はんだデイツプ等によりリードビン2を配
線パターン6にはんだ着けして配線基板4に取付けてい
た。Conventionally, in this semiconductor device, as shown in FIG. 4, through-holes 5 are provided in the wiring pattern 6 of the wiring board 4 in correspondence with the lead bins 2, and positioning stoppers 3 are provided in some of the lead bins 2. Each lead bin 2 was inserted into a through hole 5, and the lead bin 2 was soldered to a wiring pattern 6 using a solder dip or the like to be attached to a wiring board 4.
また、第5図に示すように、配線基板4にスルーホール
を設けず、配線基板4に設けた配線パターン6上に半導
体装置1のリードビン2を搭載し、リフロー等によりは
んだ付けする表面実装も行なわれている。Furthermore, as shown in FIG. 5, surface mounting is also possible in which the lead bin 2 of the semiconductor device 1 is mounted on the wiring pattern 6 provided on the wiring board 4 without providing a through hole in the wiring board 4, and soldered by reflow or the like. It is being done.
[発明が解決しようとする課題]
最近は、半導体装置や電子部品を配線基板に高密度で実
装するため、これらを配線基板の両面に取付ける両面実
装方式が進められているが、前記従来の実装方式では、
リードビン2はいずれも配線基板4の一方の面の配線パ
ターン6とだけしか接続できず、若し他方の面に設けた
配線パターンにリードビン2を接続しようとする場合は
、両面の配線パターンを導線によって接続しなければな
らず、構造が複雑になるばかりでなく、コストアップの
原因にもなっていた。[Problems to be Solved by the Invention] Recently, in order to mount semiconductor devices and electronic components on wiring boards at high density, a double-sided mounting method in which these are mounted on both sides of a wiring board has been promoted. In the method,
Each lead bin 2 can only be connected to the wiring pattern 6 on one side of the wiring board 4, and if you want to connect the lead bin 2 to the wiring pattern provided on the other side, connect the wiring pattern on both sides to the conductor. This not only complicates the structure but also increases costs.
また、第4図の例においてはリードビン2が他方の面へ
突出しているため、この面に配線パターンを形成する場
合や電子部品を取付ける場合の障害になりでいた。さら
に第5図の例においては、リードビン2の位置決めが面
倒であるばかりでなく、リードビン2は配線パターン6
に単にはんだ付けしただけなので不安定であり、輸送中
や振動・衝撃等により半導体装置1が脱落するおそれも
ある。Further, in the example shown in FIG. 4, the lead bin 2 protrudes to the other surface, which becomes an obstacle when forming a wiring pattern or attaching electronic components to this surface. Furthermore, in the example shown in FIG. 5, not only is positioning the lead bin 2 troublesome, but the lead bin 2
Since the semiconductor device 1 is simply soldered, it is unstable, and there is a risk that the semiconductor device 1 may fall off during transportation or due to vibrations, shocks, etc.
本発明は、上記の課題を解決すべくなされたもので、配
線基板の両面実装が可能であり、しかも位置決めが容易
で安定して配線基板に取付けることのできる半導体装置
の実装方式を実現することを目的としたものである。The present invention has been made in order to solve the above-mentioned problems, and an object of the present invention is to realize a mounting method for a semiconductor device that can be mounted on both sides of a wiring board, and that can be easily positioned and stably mounted on the wiring board. The purpose is to
[課題を解決するための手段]
本発明に係る半導体装置の実装方式は、リードビンのう
ち少なくとも2本を他のり−ドピンより長く構成し、配
線基板の一方の面に前記能のり一ドビンに対応して第1
の配線パターンを形成すると共に、他方の面に長いリー
ドビンに対応して第2の配線パターンを形成し、この第
2の配線パターンにスルーホールを設けたものである。[Means for Solving the Problems] A semiconductor device mounting method according to the present invention is such that at least two of the lead bins are configured to be longer than the other lead pins, and one surface of the wiring board corresponds to the lead bins. first
At the same time, a second wiring pattern is formed on the other side corresponding to the long lead bin, and a through hole is provided in this second wiring pattern.
〔作 用]
長いリードビンをスルーホールに挿入することにより、
前後左右の位置決めがなされ、他のり一ドビンが第1の
配線パターンに当接することにより上下方向の位置決め
が行なわれる。ついで、各リードビンをそれぞれ第1.
第2の配線パターンにはんだ付けする。[Function] By inserting a long lead bin into the through hole,
Positioning is performed in the front, rear, left, and right directions, and positioning in the vertical direction is performed by bringing other glue dowels into contact with the first wiring pattern. Then each lead bin is placed in the first.
Solder to the second wiring pattern.
[発明の実施例コ
第1図は本発明実施例の模式図である。なお、前述の従
来例と同−又は相当部分には同じ符号を付し、説明を省
略する。本発明においては、半導体装置1の下面に設け
た多数のり−ドビン2のうち、例えば四隅の4本あるい
は対角隅の2本の如く、少なくとも2本のリードビン2
aを他のり−ドビン2より長く形成したものである。即
ち、他方のリードビン2の長さをΩとすれば、このリー
ドビン2aの長さΩ を、g1〜g+t+α(但し、t
は配線基板4の厚さ、αは配線基板4からの突出長さ)
とする。Embodiment of the Invention FIG. 1 is a schematic diagram of an embodiment of the invention. Note that the same or equivalent parts as in the conventional example described above are given the same reference numerals, and the explanation thereof will be omitted. In the present invention, out of a large number of lead bins 2 provided on the lower surface of the semiconductor device 1, at least two lead bins 2, for example four at the four corners or two at the diagonal corners, are provided.
A is made longer than the other glue dobbin 2. That is, if the length of the other lead bin 2 is Ω, then the length Ω of this lead bin 2a is g1~g+t+α (however, t
is the thickness of the wiring board 4, α is the protrusion length from the wiring board 4)
shall be.
また、配線基板4の一方の面に、短かいリードビン2に
対応してそれぞれ配線パターン6を形成すると共に、他
方の面の長いリードビン2aに対応した位置に配線パタ
ーン6aを形成し、この配線パターン6aにスルーホー
ル5を設けたものである。Also, on one side of the wiring board 4, wiring patterns 6 are formed corresponding to the short lead bins 2, and wiring patterns 6a are formed on the other side at positions corresponding to the long lead bins 2a. A through hole 5 is provided in 6a.
上記のように構成した本発明により、半導体装置1を配
線基板4に実装するには、各配線パターン6.6aの表
面にはんだクリーム等を塗布(印刷)したのち、長いリ
ードビン2aをスルーホール5に挿入して半導体装置1
を配線基板4上に搭載する。このとき、短かいリードビ
ン2が配線パターン6に当接して上下方向の位置決めが
なされ、スルーホール5に挿入された長いリードビン2
aによって前後左右の位置決めが行なわれる。ついで、
例えばリフロー装置によってリフローすれば、短かいリ
ードピン2は配線基板4の一方の面の配線パターン6に
、長い方のリードビン2aは他方の面の配線パターン6
aにそれぞれはんだ付けされ、半導体装置1は配線基板
4上の正しい位置に実装される。According to the present invention configured as described above, in order to mount the semiconductor device 1 on the wiring board 4, after applying (printing) solder cream or the like on the surface of each wiring pattern 6.6a, the long lead bin 2a is inserted into the through hole 5. Insert the semiconductor device 1 into
is mounted on the wiring board 4. At this time, the short lead bin 2 comes into contact with the wiring pattern 6 and is positioned in the vertical direction, and the long lead bin 2 inserted into the through hole 5
Front, rear, left and right positioning is performed by a. Then,
For example, if reflow is performed using a reflow machine, the short lead pins 2 will be attached to the wiring pattern 6 on one side of the wiring board 4, and the longer lead bins 2a will be attached to the wiring pattern 6 on the other side.
a, and the semiconductor device 1 is mounted at the correct position on the wiring board 4.
この場合、長いリードピン2aは、半導体装置1の集積
回路を配線基板4の他方の面に設けた配線パターン6a
に接続する機能を有すると共に、位置決め機能も有する
ので、集積回路、パッケージ及び配線基板の設計にあた
っては、これらの機能を満足するように、長いリードピ
ン2aの位置を考慮する必要がある。In this case, the long lead pins 2a are connected to a wiring pattern 6a on which the integrated circuit of the semiconductor device 1 is provided on the other surface of the wiring board 4.
The long lead pin 2a has a positioning function as well as a connection function, so when designing integrated circuits, packages, and wiring boards, it is necessary to consider the position of the long lead pin 2a so as to satisfy these functions.
第2図は本発明の他の実施例の模式図で、本実施例にお
いては長いリードピン2bを他の短かいリードピン2よ
り太く形成して剛性を高めたもので、作用効果は第1図
の実施例の場合と同様である。FIG. 2 is a schematic diagram of another embodiment of the present invention. In this embodiment, the long lead pin 2b is formed thicker than the other short lead pins 2 to increase the rigidity, and the effect is as shown in FIG. 1. This is the same as in the embodiment.
上記の説明では、長いリードピンを2本又は4本設ける
場合について示したが、2本以上であればよく、集積回
路の設計に応じて適宜増減することができる。また他方
の面の配線パターンに接続するリードピンが1本でよい
場合は、別に1本又はそれ以上の位置決め専用のダミー
ビンを設ければよい。In the above description, the case where two or four long lead pins are provided is shown, but the number may be two or more, and the number can be increased or decreased as appropriate depending on the design of the integrated circuit. If only one lead pin is needed to connect to the wiring pattern on the other side, one or more dummy bins dedicated to positioning may be separately provided.
[発明の効果コ
以上の説明から明らかなように、本発明は半導体装置の
リードピンの一部を他のリードピンより長く構成し、ま
た配線基板の一方の面に短かいリードピンに対応して配
線パターンを形成すると共に、他方の面に長いリードピ
ンに対応して配線パターンを形成し、この配線パターン
にスルーホールを設け、このスルーホールをガイドとし
て長いリードピンを挿入し、半導体装置を配線基板に実
装するようにしたので、半導体装置の集積回路を配線基
板の両面に設けた配線パターンに直接接続することがで
き、両面実装による高密度実装が可能になった。[Effects of the Invention] As is clear from the above description, the present invention has a structure in which some of the lead pins of a semiconductor device are longer than other lead pins, and a wiring pattern is formed on one surface of the wiring board corresponding to the short lead pins. At the same time, a wiring pattern is formed on the other surface corresponding to the long lead pins, a through hole is provided in this wiring pattern, the long lead pin is inserted using the through hole as a guide, and the semiconductor device is mounted on the wiring board. As a result, the integrated circuit of the semiconductor device can be directly connected to the wiring patterns provided on both sides of the wiring board, making it possible to perform high-density mounting by double-sided mounting.
また、半導体装置は、長いリードピンによりスルーホー
ルをガイドとして配線基板に搭載されるので位置決めが
容易になるばかりでなく、長短のリードピンにより半導
体基板の両面にはんだ付けされるので取付けが安定し、
脱落するおそれがない等、実施による効果大である。In addition, the semiconductor device is mounted on the wiring board using long lead pins and through holes as guides, which not only makes positioning easier, but also allows for stable mounting because it is soldered to both sides of the semiconductor board using long and short lead pins.
Implementation has a great effect, as there is no risk of it falling off.
第1図及び第2図は本発明実施例の模式図、第3図(a
) 、 (b)はピングリッドアレイ方式の半導体装置
の一例を模式的に示した下面図及び側面図、第4図、第
5図は従来のピングリッドアレイ方式の半導体装置の配
線基板への取付例を模式的に示した断面図である。
に半導体装置、2:リードピン、2a、2b:長いリー
ドピン、4:配線基板、5ニスルーホール、6.6a:
配線パターン。
第1図
第2図Figures 1 and 2 are schematic diagrams of embodiments of the present invention, and Figure 3 (a
), (b) are bottom and side views schematically showing an example of a pin grid array type semiconductor device, and Figures 4 and 5 show mounting of a conventional pin grid array type semiconductor device on a wiring board. FIG. 2 is a cross-sectional view schematically showing an example. Semiconductor device, 2: lead pin, 2a, 2b: long lead pin, 4: wiring board, 5 varnished through hole, 6.6a:
wiring pattern. Figure 1 Figure 2
Claims (1)
板に実装するものにおいて、 前記リードピンのうち少なくとも2本を他のリードピン
より長く構成し、前記配線基板の一方の面に前記他のリ
ードピンに対応して第1の配線パターンを形成すると共
に、他方の面に前記長いリードピンに対応して第2の配
線パターンを形成し、該第2の配線パターンにスルーホ
ールを設けたことを特徴とする半導体装置の実装方式。[Claims] In a device in which a semiconductor device having a large number of lead pins arranged on a lower surface is mounted on a wiring board, at least two of the lead pins are configured to be longer than other lead pins, and a semiconductor device is mounted on one surface of the wiring board. A first wiring pattern is formed corresponding to the other lead pin, and a second wiring pattern is formed on the other surface corresponding to the long lead pin, and a through hole is provided in the second wiring pattern. A semiconductor device mounting method characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17811788A JPH0228990A (en) | 1988-07-19 | 1988-07-19 | Semiconductor device mounting method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17811788A JPH0228990A (en) | 1988-07-19 | 1988-07-19 | Semiconductor device mounting method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0228990A true JPH0228990A (en) | 1990-01-31 |
Family
ID=16042957
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17811788A Pending JPH0228990A (en) | 1988-07-19 | 1988-07-19 | Semiconductor device mounting method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0228990A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0415263U (en) * | 1990-05-26 | 1992-02-06 | ||
| US6791845B2 (en) | 2002-09-26 | 2004-09-14 | Fci Americas Technology, Inc. | Surface mounted electrical components |
| US6805278B1 (en) * | 1999-10-19 | 2004-10-19 | Fci America Technology, Inc. | Self-centering connector with hold down |
| GB2420020A (en) * | 2004-11-04 | 2006-05-10 | Richard Hoptroff | Method for mounting electrical component on printed circuit boards |
-
1988
- 1988-07-19 JP JP17811788A patent/JPH0228990A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0415263U (en) * | 1990-05-26 | 1992-02-06 | ||
| US6805278B1 (en) * | 1999-10-19 | 2004-10-19 | Fci America Technology, Inc. | Self-centering connector with hold down |
| US6791845B2 (en) | 2002-09-26 | 2004-09-14 | Fci Americas Technology, Inc. | Surface mounted electrical components |
| US7249411B2 (en) | 2002-09-26 | 2007-07-31 | Fci Americas Technology, Inc. | Methods for mounting surface-mounted electrical components |
| US7535723B2 (en) | 2002-09-26 | 2009-05-19 | Fci Americas Technology, Inc. | Surface mounted electrical components and method for mounting and retaining same |
| GB2420020A (en) * | 2004-11-04 | 2006-05-10 | Richard Hoptroff | Method for mounting electrical component on printed circuit boards |
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