JPH0229092A - Burst gate pulse generation circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a burst gate pulse generation circuit suitable for integration in household magnetic recording and reproducing devices (VTRs) and the like.

[Conventional technology]

In a VTR, when recording and reproducing a color television signal, operations such as extracting and reinserting a burst signal are necessary, and it is necessary to obtain a burst gate pulse for this purpose.

Conventionally, such a burst gate pulse generation circuit has been known in which a horizontal synchronizing pulse is delayed by a delay circuit including an LCR element or the like. That-
For example, as shown in FIG. 1, a horizontal synchronizing pulse is supplied to the input 11 of a low-pass filter 1 consisting of a resistor R, an inductance coil L, and a capacitor C, and the low-pass filter 1''C' delay is shaped to a predetermined value. Outputs a burst gate pulse having a delay time of 12 and a predetermined pulse width.
It's like getting to.

[Problem to be solved by the invention]

However, such a circuit requires elements such as a capacitor C with a relatively large capacity and a coil L with a large inductance, so even if you try to integrate the circuit, it is difficult to integrate such elements L and C. Therefore, these elements have to be externally attached to the IC as a circuit, which increases the number of external elements and increases the cost.

In addition, the delay time and threshold level are susceptible to changes due to variations in the characteristics of the R, L, and C elements and temperature dependence, and as a result, the pulse position and pulse width of the obtained gate pulse fluctuate, resulting in color burst signal During sampling, part of the video signal may be missing, or part of the video signal may be picked up incorrectly, making it impossible to obtain correct phase information, causing distortions such as uneven hue.

Furthermore, the time relationship between the horizontal synchronizing pulse and the burst signal may be different during recording and playback on a VTR, and in such cases the position of the gate pulse must be changed, but conventional A circuit consisting of R, L, and C elements has the drawback that accurate switching is difficult and the structure is complicated.

An object of the present invention is to provide a burst gate pulse generation circuit that eliminates the drawbacks of the prior art described above, can obtain accurate gate pulses with stable characteristics, can be easily integrated into an IC, and can easily switch the pulse position. There is something to do.

[Means to solve the problem]

In order to achieve this object, the present invention is characterized in that a gate pulse is obtained from a horizontal synchronizing signal by a digital method.

[Effect]

In home VTRs, etc., a so-called color signal low-frequency conversion method is adopted, in which the color signal is converted to a low frequency range and recorded, and for high-density recording, the phase of the low-frequency converted color signal is converted into one horizontal line. Recording is performed with a 90° shift during each scanning period (IH). Therefore, the horizontal scanning frequency fH
The color signal is converted to a frequency band of 630 KHz, which is 40 times the frequency band of 630 KHz.
A reference oscillator with a frequency of 2.52 MHz, which is four times KHz, is provided, and its output is divided by 1/4 to generate 4 oscillators, each with a 90° phase difference.
There is a system in which two signals are created and used by switching between them for each IH.

Therefore, in the present invention, good results can be obtained by utilizing the output of this 2.52 MHz reference oscillator.

〔Example〕 Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 shows an embodiment in which the present invention is applied to a VTR having a 2.52 MHz reference oscillator as described above, where 2 is a phase detection circuit, and 3 is a 2.52 MHz voltage controlled oscillator (VC).
○), 4 is a 174 frequency divider, 5 is a 1740 frequency divider, 6 is a horizontal synchronization game for extracting only the horizontal synchronization signal from the composite synchronization signal 1-17 is a comparison wave generator, 8 is a phase selection circuit, 1
3 is a clock pulse setting unit, 14 is a synchronous 1/4 frequency divider circuit that becomes the first frequency dividing means, 15 is a synchronous 1/6 frequency divider circuit that is the second frequency divider, and 16 is a reset. This is a pulse setting section. In addition, 9 is a control voltage terminal for controlling vC○3 as necessary, 10 is a terminal to which a composite synchronization signal separated from the television signal is supplied, 11 is a horizontal synchronization pulse input, and 12 is a burst gate. This is a pulse output.

1 when 2.52MHz signal 3a appears from VCO3
A signal 4a of 630 KHz, that is, 40 fH, is obtained at the output of the 74 frequency divider 4, and this is divided by a frequency of 1/40 and divided into h
f H signal is supplied to the horizontal synchronization gate 6, and the vertical synchronization signal and equalization pulse are removed from the composite synchronization signal from the terminal 10, and only the horizontal synchronization pulse is extracted and supplied to the phase detection circuit 2.

Further, the f i signal from the frequency divider 5 is waveform-shaped by the comparison wave generator 7 and is supplied to the phase detection circuit 2, where the phase is compared with the horizontal synchronizing pulse. Then, the phases are compared and a control voltage corresponding to the difference is given from the phase detection circuit 2 to the VCO 3, so in the end, the 2
．． The 52 MHz signal 3a is a signal whose phase is synchronized with the horizontal synchronizing pulse of the synchronizing signal supplied to the terminal 10.

The signal of this VCO 3 becomes a signal 4a whose frequency is divided by 1/4 and is outputted from the phase selection circuit 8 as a signal 40f, which is used in the color signal low frequency conversion method.

Therefore, the burst gate pulse generating circuit according to the present invention utilizes the signal 3a from the VCO 3 as a clock pulse, and supplies this to the tarock pulse setting section 13 together with the horizontal synchronizing pulse from the input 11. The clock pulse from the setting section 13 is supplied to a 174 frequency dividing circuit 14, which is a first frequency dividing means, and sets the delay time of the burst gate pulse from the horizontal synchronizing pulse. Then the output is the second
It is supplied as a clock pulse to the 1/6 frequency dividing circuit 15, which is a frequency dividing means, and sets the pulse width of the burst pulse, and also gives a signal to the reset pulse setting section 16.
A series of operations that start at the rising edge of the horizontal sync pulse are completed before the next sync pulse rises.

Next, details of one embodiment of the burst gate pulse generation circuit according to the present invention will be explained with reference to FIG.

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ND gate, 19 is a NAND gate for gating the clock pulse 3a, 20 and 23 are inverters, 21 is a delay circuit formed by connecting, for example, five inverters in series, and 22 is a NAND gate.

Further, Fl and F2 constitute a first frequency dividing circuit 14, and 1/
A D-type flip-flop to which the same clock for frequency division by 4 is input, F3. F4 and F5 constitute the second frequency dividing circuit 15, and are D-type flip-flops to which the same tarlock for performing 1/6 frequency division is input. Therefore, the first frequency dividing circuit 14 (Fl, F2) and the second frequency dividing circuit 15 (F3, F4, and F5) each operate with the same clock, and are synchronous frequency dividing circuits.

Note that 24 is a terminal connected to the output of the second VCO 3 and supplied with the clock pulse 3a.

Next, the operation shown in FIG. 3 will be explained using the waveform diagram shown in FIG. 4.

NAND gates 17 and 18 trigger negative pulses? p! ^
%j R~S furinofurotsuno lba and one terminal 11
NAN
It is reset by a reset pulse of opposite polarity from the D gate 22, and an AND gate formed by a NAND gate 19 and an inverter 20 provides a clock pulse 3a to flip-flops (hereinafter simply referred to as FF) Fl and F2.

Therefore, the water 1L synchronization pulse shown by waveform i in FIG. 4 is at time t. When the clock pulse of waveform a starts to be supplied to FFFI and F2, a pulse of waveform a appears at the Q output of FFF Fl, and this is supplied to the D input of FFF2, so its outputs Q and Q Pulses of waveforms C and d are obtained. At this time, 2 of the waveform d of the output Q of FFF2
The rising edge of the eighth pulse rises at the rising edge of the eighth pulse after the clock pulse a is added at time tl, and since the period of the clock pulse a is 0.4 μs, the period of the clock pulse a is 0.4 μs. 2. From the rising time of the horizontal synchronization pulse.
This occurs after a delay of 8 μs. Therefore, the output Q of FFF2 is used as the rising edge signal of the burst gate pulse.
It is applied to the frequency divider circuit 5 of FFFI and 4 to the D input of FFFFl so that the operations of FFFI and F2 are performed with a one-clock shift. Since this first frequency divider circuit is a synchronous frequency divider, the output delay with respect to the clock can be achieved by the minimum flip-flop stage as a frequency divider circuit.

The signal of waveform d of the Q output of FFF2 is the signal of waveform d of the first and second FF, that is, the Q output of F3 and F4 is the D of the next stage FF.
Since the Q output of the third FF, i.e., F5, is connected to the input, the Q output of the third FF, i.e., F3, is supplied to the three FFs, i.e., the clock power CL of F3-F5, which is connected to the first FF, i.e., F3. The Q outputs of FFF3 to F5 each have a waveform et ftg. Now, if we pay attention to the fourth Q output of FFF, it is clear from the waveform f that the time t0
It rises when 68 clock pulses a are applied, and then falls when 13 tarok pulses a are applied. Therefore, the signal of waveform f, which is the Q output of FFF4, has a delay of 2.8 μs from time t, that is, when the horizontal synchronization pulse j is generated.
It then becomes a pulse with a width of 4.8 μs, which is understood to be the optimal pulse for the gate of the burst signal. Therefore, if the Q output of FFF4 is taken out as output 12, a burst gate pulse can be obtained. Since this second frequency divider circuit is also a synchronous frequency divider, the delay of the output with respect to the clock input is only a portion of the flip-flop, like the first frequency divider circuit. In this way, the output can be obtained with only a delay of two stages of flip-flops in total, making it possible to reduce the influence of the delay time of the flip-flops.

By the way, if this continues, signals of waveform f will appear one after another during IH until the next horizontal synchronizing pulse is given, so the Q output of FFF5 is added to one input of the NAND gate 22, and the odd-numbered The signal is supplied to the other input of the gate 22 via a delay circuit 21 consisting of an inverter.

As a result, the rising part of the Q output of FFF5, that is, the Q
From the falling part of the output waveform g, a reset pulse in the negative direction with a pulse width corresponding to the delay time of the delay circuit 21 is obtained at the output of the NAND gate 22, so this is inverted by the inverter 23 to form the waveform. As the reset pulse shown, in addition to the reset input R of all FFF1 to F5, all these FFs are reset, and the R-8FF
The input of the NAND gate 18 forming the F
FF reset input to reset this FF and NA
The AND gate consisting of the ND gate 19 and the inverter 20 is closed to stop the supply of clock pulses.

As a result, when a horizontal synchronizing pulse appears at the input 11, only one pulse with a pulse width of 4.8 μS appears at the output 12 with a delay of 2.8 μS, and the IH
No output appears at output 12 until a horizontal sync pulse appears at input 11 again after this period.

As described above, according to this embodiment, the burst gate pulse can be obtained digitally by dividing the clock pulse from V and CO3, which are synchronized by the horizontal synchronizing pulse, using a synchronous frequency divider. Therefore, the delay time from the horizontal synchronizing pulse of the gate pulse obtained at the output and its pulse width are precisely defined by the clock pulse, and are always constant without being affected by variations in circuit elements or temperature changes. Accurate burst game-one pulses can be obtained.

FIG. 5 shows another embodiment of the invention. The embodiment shown in FIG. 5 differs from the embodiment shown in FIG.

The reset side output of the R-8FF consisting of NAND gates 17 and 18 that constitutes the clock pulse setting circuit 13 is used together with the reset pulse from the inverter 23 to
Supplied to the reset input of FFI~F5, Q of FFF4
After the signal f appears at the output, a reset pulse h appears at the output of the inverter 23, and all FFF1 to F5 are reset, and at the same time, R-8FF consisting of NAND gates 17 and 18 is also reset, but this R-SFF The output on the reset side is e, followed by the reset pulse h from the collar 97, 3.
5 is applied to the reset manual power, so that it does not operate even if the clock pulse 3a is supplied to FFF i and p'2 until the horizontal synchronization pulse is supplied to the input 11 again after LH has elapsed. The operation is the same as the embodiment of FIG. 3 to obtain a precise burst gate pulse at output 12. I can do two things.

FIG. 6 shows yet another embodiment of the invention. The difference between the embodiment of FIG. 6 and the embodiment of FIG. 3 is that the switching circuit 25
It is also possible to select C by switching the delay time of the gate pulse.

In a VTR, the general brightness (, -i) and color signals are separated and processed separately, so the delay time of the burst signal from the horizontal synchronizing pulse differs during recording and playback. Become something.

Therefore, it is desirable to be able to switch the delay time of the burst gate pulse between recording and reproduction.

Therefore, in the embodiment shown in FIG. 6, a switching circuit 25 consisting of a N A N D gate 30°31.32 is provided, and the tallock pulse for the 1/6 frequency dividing circuit 15, which is the second frequency dividing means, is transferred to the first frequency dividing means. F constituting the 1/4 frequency divider circuit 14
It is possible to select either the Q output or the Q output of FF2. During recording, a voltage is supplied to one of the six gates of the NAND gate 31 and the Q output of FFF2 is extracted as a tarok pulse, and during playback, a voltage is applied to one of the NAND gates 30 to obtain the Q output of i''FF2. The waveform diagram in Figure 4 becomes 1 by extracting it as a clock pulse.
- As is clear, the tarok inputs of F F' F 3 to F5 are switched to either waveform C or d, and when switched to waveform C, the rising edge of the Q output of F The delay time of the burst gate pulse can be optimized and accurately changed in response to switching between recording and reproduction of the VTR. I can do two things.

In each of the embodiments of the present invention described above, the clock pulse is obtained from the 2.52 MHz VCO for color signal low frequency conversion, but the clock pulse is obtained from the 3.58 MHz VCO output for the color subcarrier. In this case, the frequency division ratio of the first frequency dividing means 15 may be set to 1/6, and the width of the burst gate pulse obtained thereby will be approximately 5 μs. Since it is possible to obtain a burst gate pulse generation circuit which is sufficiently practical, it can be applied to many VTRs and a great effect can be obtained.

Further, in the above embodiment, a D type FF was used as the FF, but it is obvious to those skilled in the art that the FF is not limited to this. You can also get the same effect.

[Effects of the Invention] As explained above, according to the present invention, the burst 1-gate pulse is digitally calculated by counting the clock pulses from the reference oscillator whose phase is synchronized with the horizontal synchronizing pulse using a synchronous frequency divider. Since the configuration is configured to generate a gate pulse, it is possible to always obtain an accurate gate pulse without being affected by variations in the characteristics of the elements used or changes in conditions during use.

In addition, since it is not necessary to use elements such as LCi elements that are extremely difficult to integrate into an IC, the number of external parts required for integration into an IC is reduced, reducing factors that increase costs and reducing costs. Advantages such as easy accurate switching of gate pulse generation conditions can be obtained.

In addition, many home-use VTRs use a color signal low-frequency conversion method, so clock pulses can be obtained from a VCO, etc. for this purpose, and the configuration can be shared, making it possible to further reduce costs. becomes.

[Brief explanation of the drawing]

Fig. 1 is a wiring diagram of a conventional circuit for obtaining a burst gate pulse from a horizontal synchronizing pulse, Fig. 2 is a block diagram of a portion including a burst gate pulse generation circuit of a VTR to which the present invention is applied, and Fig. 3 is a diagram of the present invention. A four-line diagram of a burst gate pulse generation circuit according to one embodiment, FIG. 4 is a waveform diagram for explaining its operation, and FIG. 5 and FIG. FIG. 1 is a wiring diagram of a pulse generation circuit. 3... Voltage controlled oscillator (VCO), 13... Clock pulse setting section, I4... 1/4 frequency dividing circuit serving as first frequency dividing means. 15... 1/6 frequency dividing circuit, 1G, which is the second frequency dividing means
...Reset pulse setting section. 1,000 synchronized + (11 people)

Claims (1)

[Claims] 1. In a burst pulse generation circuit for obtaining a burst gate pulse having a predetermined delay time and a predetermined pulse width from a horizontal synchronizing signal; An oscillation means that oscillates at an oscillation frequency of a large integer), an oscillation output signal and a horizontal synchronization signal of the oscillation means are input, a phase comparison between the oscillation output signal and the horizontal synchronization signal is performed, and a phase control signal is supplied to the oscillation means. and a clock pulse generating means for generating a clock pulse synchronized with the horizontal synchronizing signal, the pulse position of which is determined by the horizontal synchronizing signal at predetermined time intervals, and having a sufficiently shorter period than the horizontal synchronizing signal. ; A frequency dividing means which receives the clock pulse from the clock pulse generating means as a clock input; A frequency dividing operation of the frequency dividing means is performed by starting supply of a clock to the frequency dividing means in synchronization with a horizontal synchronizing signal; Frequency division control that stops the frequency dividing operation of the frequency dividing means by stopping the clock supply to the frequency dividing means after a predetermined time and resetting the frequency dividing means with the output of the frequency dividing means. A burst gate pulse generation circuit equipped with means. 2. In claim 1, the frequency dividing means includes first and second frequency dividing circuits, and the clock input terminal of the first frequency dividing circuit receives a clock from the clock pulse generating means. A pulse is input, the output signal of the first frequency divider is input to the clock input terminal of the second frequency divider, and the first and second frequency dividers perform frequency division in synchronization. A burst gate pulse generation circuit characterized by: 3. In claim 2, each of the first and second frequency dividing circuits has a plurality of flip-flops connected in series, and the clock input terminal of the flip-flop of the first frequency dividing circuit is A clock pulse from the clock pulse generation means is input to each of the clock pulse generating means, and an output signal of the first frequency divider circuit is input to each clock input terminal of the flip-flop of the second frequency divider circuit. Burst gate pulse generation circuit.