JPH02294113A - Pulse generation circuit - Google Patents

Abstract

PURPOSE:To reduce an error in a duty ratio and to vary the duty ratio optionally by deciding a number to be counted of a 2nd counter in response to the duty ratio from a count counted by a 1st counter. CONSTITUTION:When a 1st pulse of an input pulse train goes to a high level, the count of a clock pulse is started by a 1st counter 1 and when the level of a 2nd pulse goes to H, the count is stopped and also a new count is started. Simultaneously, the count is started by the 2nd counter 2 and an output pulse of an output circuit 5 goes to an H level. Then based on the count by the 1st counter 1, the counted value n1 of the 2nd counter 2 is decided in response to the duty ratio of a computing element 3, set to a comparator 4 and when the count of the 2nd counter and the value n1 are coincident, the output pulse of the output circuit 5 goes to a low level. Thus, the error in the duty ratio is reduced and the duty ratio is varied optionally.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a pulse generation circuit.

[Prior Art] As a conventional pulse generating circuit, an encoder is known which is constituted by an optical slit disk, a light emitting element, a light receiving element, and a converter. The duty ratio of the output pulses of the encoder configured in this manner is usually determined based on whether the input voltage exceeds the threshold voltage of the converter, that is, a set reference voltage.

[Problems to be Solved by the Invention] However, in the conventional pulse generation circuit, the duty ratio is determined based on the magnitude of the reference voltage, so the following (1)
)． There were problems like (2).

(1) When the variations between individual elements are large, attempting to suppress the variations within a predetermined range requires precise adjustment, which increases costs.

The error in the duty ratio is usually about 30 zero, which can be reduced to 1
Reducing the value to 0 or less will result in a significant cost increase.

(2) Once the duty ratio is determined, it is impossible to arbitrarily change it later.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and provide a pulse generation circuit that reduces errors in the duty ratio and can arbitrarily change the duty ratio.

[Means for Solving the Problems] To achieve such an object, the present invention provides a first count that counts reference pulses from the arrival of the first input pulse until the arrival of the second input pulse. means for determining the number of the reference pulses to be counted from the number of counts counted by the first counting means according to a predetermined duty ratio; a second counting means for counting, and when the second counting means starts counting, changes the output signal level from the first level to the second level, and counts only the number of counts determined by the determining means; , and signal output means for changing the output signal level from a second level to a first level.

[Function] In the present invention, the reference pulse is counted by the first counting means from the arrival of the first input pulse until the arrival of the second input pulse, and the reference pulse is counted from the count number counted by the first counting means. The number of reference pulses to be counted is determined by the determining means in accordance with a predetermined duty ratio, and the number of reference pulses to be counted is determined by the determining means as the second reference pulse.
When the counting means counts, when the second counting means starts counting, when the signal output means changes the output signal level from the first level to the second level, and when the count number determined by the determining means is counted,
The signal output means changes the output signal level from the second level to the first level.

[Embodiments] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows an embodiment of the invention.

Reference numeral 1 designates a first counter as a first counting means, which counts reference pulses from the arrival of the first input pulse until the arrival of the second input pulse. Reference numeral 3 denotes an arithmetic unit as a determining means, which determines the number of reference pulses to be counted from the number counted by the first counter 1 in accordance with a predetermined duty ratio. 2 is the second
The second counter serves as a counting means and counts the reference pulses by the number to be counted determined by the arithmetic unit 3. A comparator 4 compares the count value of the second counter 2 with the number to be counted determined by the arithmetic unit 3. Reference numeral 5 designates an output circuit as a signal output means. When the second counter 2 starts counting, the output signal level is set to high level, and when the count number determined by the calculator 3 has been counted, the output signal level is set to Takai No. 8 level. is set to low level.

In the tree embodiment, the duty ratio of the input pulse is 0.9, the pulse period fluctuates within ±10%F, and the fluctuation period is 10 times the pulse period. Next, the operation when the duty ratio of the pulse train is set to "1" will be explained.

When the first pulse of the input pulse train goes to high level (}I), the first counter 1 starts counting clock pulses, and then the second pulse of the input pulse goes to rH,
When , the clock pulse count is stopped and a new clock pulse count is started.
At the same time, the second counter 2 starts counting clock pulses. Also, the output pulse of the output circuit 5 is rH
,become.

Then, the count value by the first counter l is held,
Based on this held count value, the calculator 3 calculates
The number to be counted by the second counter 2 is determined according to the duty ratio, and is set in the comparator 4. In this case, since the duty ratio is "1", the final count value is divided by N-2 to obtain n+(one count value/2).

Next, the comparator 4 compares the count 1 value of the second counter 2 with 01, and when the count value and 11 match, the output pulse of the output circuit 5 is made low (L).

Thereafter, when the third input pulse becomes "11", counting by the first counter 1 is stopped. At the same time, counting of clock pulses is newly started, and the output pulse of the output circuit/circuit 5 is set to rH.

Thereafter, if the above operation is repeated, a pulse train delayed by one cycle from the input pulse train will be output.

The error in the duty ratio of the output busle is affected by the amount of variation in the cycle of the input pulse and the cycle of variation.

If the period of the manual pulse is constant, the only error in the duty ratio of the output pulse is a rounding error in the count value. On the other hand, when the period of the input pulse fluctuates as described above, the error is approximately as follows.

Valus Shuho can be expressed as in equation (1).

T (t) = To {t+(ΔT/To) sin
(11 t)=T0{1+(ΔT/To) si'
n(ωo/10)t) = (1) Here, Ding. Two fundamental periods ΔT: Error amount of the period ω0: Fundamental frequency of the input pulse ω: Fluctuation frequency of the error period The error in the duty ratio of the output pulse is caused by the difference between temporally adjacent pulse periods, so the error δ is δ=7 ((n◆1) Tol − T (nTo
), (11 0 = (2?T /To), δ= To {t+ (ΔT/To) sin(ωo/
10) (n+1)To}-To{14(ΔT/To)
sin (ωo/10) nT. }=ΔT(sin
((n+1) yr/5) − sin(nπ
/5)))? 2 ΔT sin(π/10)cos(
(2n+1)yr/10}δ@■ Cape 0.62ΔT.

The maximum value of the duty ratio is 62% of the periodic error amount, so in the case of this input pulse train, it is 6.2%F. When the duty ratio is smaller than 0.938, it can be said that the present invention is effective.

In addition, in the tree example, in order to make the explanation easier to understand, the first
Although an example using two counters, a counter and a second counter, has been described, in reality, it is possible to perform the same operation with one counter. In addition, since this embodiment is configured as described above, a circuit is added compared to the conventional example, but there is almost no increase in cost.
The error in duty ratio can be suppressed to lO%i.

Furthermore, this characteristic is hardly affected by the environment such as temperature.

In particular, it is effective for printing control of a printer that prints according to pulse width.

(Other examples) FIG. 2 shows another embodiment of the invention.

At the same time that the first pulse of the input pulse train becomes "]1", the first counter 1 starts counting clock pulses, and when the second pulse becomes rH, it stops counting and starts counting a new clock pulse. The output pulse of the output circuit 7 is set to rH. Then, the count value is held, and the value is calculated by the calculator 3 according to the output duty ratio. The calculated value nl is input to a second counter, and is counted down by a clock pulse. Then, when the count value of the second counter 6 reaches "0", the output pulse of the output circuit 7 is set to "L".

When the third human power pulse becomes "H", the first counter 1
stops counting and simultaneously starts counting anew. At this time, the output voltage of the output circuit 7 is set to rH.

Thereafter, by repeating the above operations, a pulse train delayed by one cycle from the input pulse train is output.

Since this embodiment is configured as described above, the effects of this embodiment are not physically different from those of the first embodiment.

[Effects of the Invention] As explained above, according to the present invention, with the above configuration, the error in the duty ratio can be reduced with almost no increase in cost, and the duty ratio can be changed arbitrarily. There is an effect.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a pulse generating circuit according to one embodiment of the present invention, and FIG. 2 is a block diagram showing a pulse generating circuit according to another embodiment of the present invention. DESCRIPTION OF SYMBOLS 1...First counter, 2...Second counter, 3...Arithmetic unit, 4...Comparator, 5...Output circuit.

Claims (1)

[Claims] 1) A first counting means for counting reference pulses from the arrival of the first input pulse until the arrival of the second input pulse; and the number of counts counted by the first counting means. a determining means for determining the number of the reference pulses to be counted according to a predetermined duty ratio from the determining means; a second counting means for counting the reference pulses by the number to be counted determined by the determining means; and the second counting means. When the count is started, the output signal level is changed from the first level to the second level,
A pulse generating circuit comprising signal output means for changing the output signal level from a second level to a first level when the count number determined by the determination means is counted.