JPH028492B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a frequency multiplier circuit, and more particularly to a frequency multiplier circuit that generates an output pulse n times as large as an input pulse.

The prior art will be explained with reference to FIGS. 1 to 4.

FIG. 1 is a block diagram of one embodiment of a conventional frequency multiplier circuit. In the figure, 1 is a high-frequency oscillator that measures the period of the input pulse and creates a reference pulse for the down counter, 2 is a frequency divider circuit that divides the reference pulse by a multiplier (n), and 3 is a frequency divider that divides the reference pulse by a multiplier (n). The count value is reset to "0" by a reset pulse synchronized with the input pulse, and the output of the frequency divider circuit becomes 1.
An up counter that counts up by 1 for each pulse and counts the cycle of the input pulse; 4 is a register that stores the value just before the up counter 3 is reset by the set pulse that occurs immediately before the reset pulse; A down counter in which the stored value is set and is decremented by 1 each time the oscillator pulse is generated (countdown), and when the value reaches "0", an output is generated and the value stored in the register 4 is set again. , 6 is a timing circuit that generates a set pulse at the rising edge of the input pulse and generates a reset pulse after a certain period of time.

FIG. 2 is a time chart showing the entire operation of FIG. 1. The overall operation will be explained with reference to FIG.

The high frequency oscillator output becomes a pulse with a period of 1/f ₀ as shown in a in the figure. In the frequency divider circuit 2, the count value is increased by 1 like b every cycle of 1/f ₀ , and when the count value reaches n, it overflows due to the pulse of the next high frequency oscillator output and generates an output like c. At the same time, the count value becomes "0" and counting starts again. That is, the output becomes a pulse whose frequency is divided by 1/n. The up counter 3 is reset to "0" at the rising edge of the input pulse, and is set to 0 for each output pulse of the frequency divider circuit 2.
Increase the count value as e by D ₁ or D ₂ ,
Count as D ₃ etc. It is reset to "0" again at the rising edge of the input pulse. The values D ₁ , D ₂ , and D ₃ immediately before being reset are stored in the register 4 one after another like f.

These D ₁ , D ₂ , and D ₃ are data indicating the generation timing (occurrence cycle) of the input signal. In terms of the measurement period, D ₁ , D ₂ , and D ₃ are the values obtained by measuring the input pulse generation period 1/fi with a periodic pulse of n/f ₀ , that is, the value obtained by dividing 1/fi by n/f ₀ . The value of the quotient (however, the fractions below the decimal point are rounded down. Here, the fractions below the decimal point always occur unless 1/fi is an integral multiple of n/f _0. ) The relationship between D ₁ to D ₃ and f ₀ , fi, and n is D ₁ ≒D ₂ ≒D ₃ ≒f ₀ /nfi (1) if the period of the input signal does not change much.

The memorized values _D1 to _D3 are set in the down counter 5, and the values are decreased by 1 every 1/ _f0 period as shown in the figure g. When the value reaches "0", an output pulse like h is outputted. When the signal is generated at the terminal, the value of register 4 is set again. As a result, the down counter 5 outputs pulses with periods t ₁ , t ₂ , and t ₃ . t ₁ , t ₂ ,
The relationship between t ₃ D ₁ ~ D ₃ , f ₀ , n, and fi is t ₁ = D ₁ /f ₀ t ₂ =D ₂ /f ₀ t ₃ =D ₃ /f ₀ ...(2) (1), From equation (2), t ₁ ≒t ₂ ≒t ₃ ≒f ₀ /nfi・1/f ₀ =1/nfi (3). That is, the frequency of the output pulse is multiplied by n times the frequency fi of the input pulse.

Referring to FIG. 3, the operation of resetting and setting the up counter 3 and register 4 at the rising edge of the input pulse will be explained. When the input pulse rises as shown in Figure 3b, the pulse width as shown in c
The timing circuit 6 generates a pulse S of _T1 . This pulse is used as a set signal for the register 4, and the count value _D2 of the up counter 3 is set (stored) in the register as f. When the set output S is generated, the timing circuit generates a pulse R having a pulse width _T3 after _T2 hours. This pulse R is used as a reset pulse for the up counter 3, and the count value of the up counter 3 is reset to "0" as indicated by e.

The drawbacks of the prior art will be explained with reference to FIG. 4, which is an enlarged view of the dotted line area A in FIG.

As shown in Figure 4b and d, the input pulse is transmitted to the frequency dividing circuit 2.
Suppose that the count value of is n ₁ (a value smaller than n). This startup means that a new input signal has been input. At that time, the count value of the up counter is assumed to be _D2 . On the other hand, when the period of the input pulse is measured, it should increase as shown by the dotted line in the figure e, so it becomes f ₀ /nfi. Therefore, the period of the output pulse becomes smaller by the difference (f ₀ /nfi−D ₂ ).
The frequency becomes higher. Therefore, the down counter 5
The disadvantage is that the number of output pulses is not n times the number of input pulses, but n+Δn times the number of input pulses.

This drawback is that when used as a reference pulse generation circuit for an automatic pulse phase shifter, the output pulses of the automatic pulse phase shifter will be out of phase. Furthermore, when used for frequency or speed detection, the detected value will vary every sampling.

SUMMARY OF THE INVENTION An object of the present invention is to provide a frequency multiplier circuit that does not have the above drawbacks and generates output pulses n times the number of input pulses.

The idea of the present invention is as follows.

The count value of the frequency divider circuit when the input signal rises is
n ₁ (n ₁ < n), and the count value of the up counter is D ₁ (the above
D ₂ ). On the other hand, if n is not n ₁ , the count value of the up counter should be D ₁ +1. With respect to n ₁ , the period is too short if only D ₁ is used, as described above, and the period is too long if only D ₁ +1 is used. Therefore, n counts should be made between D ₁ and D ₁ +1, and since the period and frequency are inversely proportional, during this n count, D ₁ should be (n-n ₁ ) number of times, and (D ₁ +1) is distributed n ₁ times. That is, it can be expressed as _D1 + _n1 /n= _D1 (n- _n1 /n)+( _D1 +1) _n1 /n. This is substantially the same as setting D ₁ +n ₁ /n, and the error due to n ₁ can be substantially eliminated.

Based on this idea, in the present invention, 0 to (n-
n ₁ ), D ₁ is set as the preset value of the down counter, and (n - n ₁ +1) to n
Until then, we decided to set (D ₁ +1).

An explanation will be given according to an example.

FIG. 5 is a block diagram showing one embodiment of the present invention, and FIG. 6 is an explanatory diagram of its operation. In FIG. 5, the input signal, the multiplied pulse, is input to a timing circuit 6, which generates a set (preset) S times reset R timing signal. Specifically, the timing is as shown in FIG. The reset frequency divider 7 divides the output pulse of the pulse circuit 1 into 1/n. Furthermore, this frequency divider 7 is reset each time a multiplied pulse is input (started).

The up counter 3 counts the 1/n frequency divided output from the frequency divider 7 for one period of the multiplied pulse. The correction circuit 8 presets the count value of the frequency divider 7 every time the multiplied pulse is input, and outputs the multiplied pulse (second count up signal) of the down counter only when the preset value is less than or equal to the value n. Count. Then, when the value n is reached, the correction circuit 8 generates an output pulse (first count up signal) and sends it to the register 9.

The register 9 with an up counter presets the count value of the up counter 3 every time a multiplied pulse is input. Furthermore, this register 9 counts the output pulses of the correction circuit 8 to a preset value.

The down counter 5 presets the count value of the register 9 every time its own multiplied pulse output is generated.
Then, the preset value is counted down using the output pulse of the pulse circuit 1. When it becomes zero, a multiplied pulse 5a is generated. This multiplied pulse becomes the multiplied pulse to be found.

Further, the operation will be explained in detail with reference to FIG.

Now, if the period is not constant but slightly fluctuates, and the input signal rises when the count value of the frequency divider 7 is n ₁ (however, n ₁ < n), the multiplied output of the down counter 5 is the same as in the conventional example. is a period shorter than the reference (t ₁₀ )
(Figure 6).

However, in this embodiment, this short period (t ₁₀ )
does not continue until the next new input signal is input (n−
n ₁ ), after which a long period (t ₁₁ ) continues until n is reached. This is because the correction circuit 8 works.

That is, the correction circuit 8 presets the count value n ₁ of the frequency divider 7, but since n ₁ <n, the correction circuit 8
Further, (n-n ₁ ) multiplied output pulses from the down counter 5 are counted up, and when n is counted, a +1 count up signal as shown in FIG. 6f is output. In response to this, register 9 adds +1 to D ₁ to obtain a count value of D ₁ +1. In the following
A multiplied pulse corresponding to D ₁ +1 is generated from the down counter 5 (FIG. 6h, i). This D ₁ +1 is
Since the value is large compared to D ₁ , the multiplied pulse itself also has a long period (t ₁₁ ).

Thus, if the period from the arrival of a new input signal to the arrival of the next new input signal is t ₀ , then this
t ₀ is a mixture of t ₁₀ and t ₁₁ with an inverse proportional relationship of (n-n ₁ ) and n ₁ , respectively, and t ₀ = t ₁₀ × (n-n ₁ ) + t ₁₁ × n ₁ =D ₁ /f ₀ ×(n−n ₁ )+D ₁ +1/f ₀ ×n ₁ =1/f ₀・n・(D ₁ +n ₁ /n)……(4). On the other hand, D ₁ +n ₁ /n becomes D ₁ +n ₁ /n=f ₀ /fin (5). Therefore, equation (4) becomes t ₀ =1/f ₀ ·n·(f ₀ /fin) = 1/fi (6). That is, the period in which 0 to n output pulses are generated is the period 1/fi of the input pulse. In other words, substantially n output pulses are generated for one input pulse.

Therefore, according to the present invention, it is possible to generate an output with a number of pulses n times the number of input pulses.

As described above, according to the present invention, input pulses can be multiplied with high precision.

[Brief explanation of drawings]

Fig. 1 is a block diagram of the conventional example, Fig. 2 is an overall operational diagram of the conventional example, Fig. 3 is an operational diagram explaining the detailed timing of the timing circuit, and Fig. 4 is an operational diagram explaining the drawbacks of the conventional example. , FIG. 5 is a block diagram showing one embodiment of the present invention, and FIG. 6 is an explanatory diagram of the operation of the present invention. 1... High frequency oscillator, 2... Frequency divider circuit, 3...
Up counter, 4... Register, 5... Down counter, 6... Timing circuit, 7... Frequency divider with reset, 8... Correction circuit, 9... Register with up counter.

Claims (1)

[Claims] 1. A pulse circuit that outputs a pulse of a constant frequency, and a first pulse circuit that generates a frequency-divided output by 1/n the output pulse of the pulse circuit and that is reset every time a multiplied pulse is input. a second counting means for counting the frequency-divided output pulse of the first counting means for one period of the multiplied pulse; a third counting means which presets the count value of the second counting means and inputs the first count up signal and accumulates the count to the preset value; At the same time, only when the preset value is less than or equal to the value n, the second count up signal is input to accumulate the count to the preset value, and when the count value reaches the value n, an output pulse is generated and the output pulse is a correction means for providing a count up signal of 1, and a count value of the third counting means each time a self-multiplied pulse is generated, and inputting the output pulse of the pulse circuit as a count down signal to set the count value to the preset value. a fourth counting means that counts down from the preset value, generates a multiplied pulse when the preset value counting ends, outputs the multiplied pulse as the second count up signal, and outputs the multiplied pulse to the outside as the multiplied pulse; Frequency multiplier circuit.