JPH02295151A - Manufacture of dielectric isolating substrate - Google Patents

Manufacture of dielectric isolating substrate

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Publication number
JPH02295151A
JPH02295151A JP11508389A JP11508389A JPH02295151A JP H02295151 A JPH02295151 A JP H02295151A JP 11508389 A JP11508389 A JP 11508389A JP 11508389 A JP11508389 A JP 11508389A JP H02295151 A JPH02295151 A JP H02295151A
Authority
JP
Japan
Prior art keywords
film
substrate
oxide film
shallow
isolation island
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11508389A
Other languages
Japanese (ja)
Other versions
JP2667708B2 (en
Inventor
Taiji Usui
臼井 太二
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP11508389A priority Critical patent/JP2667708B2/en
Publication of JPH02295151A publication Critical patent/JPH02295151A/en
Application granted granted Critical
Publication of JP2667708B2 publication Critical patent/JP2667708B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

PURPOSE:To prevent isolated shallow islands from deforming by etching a region part in a desired thickness in a state that the side face of a shallow isolated island forming region part of a board is protected by an oxide film. CONSTITUTION:An SiO2 film 22 remains under a CVD SIN film 23 and at a deep isolated island forming region, and is removed from a V-shaped groove forming region part. Then, with the remaining films 22, 23 as masks an isolating V-shaped groove 23 is formed at a semiconductor substrate 21 by alkaline anisotropic etching. Thereafter, the film 22 is removed to expose a deep isolated island forming region part 25 of the substrate thereunder. Then, it is thermally oxidized with the film 23 as a mask, and a LOCOS oxide film 26 is formed on the front face of a first region 25 and the side face of a V-shaped groove 24. Then, the film 26 is used as a protective film of the substrate 21, the two layers of the films 23, 22 are removed by etching, and the front face of a shallow isolated island forming region part 27 of the substrate thereunder is exposed.

Description

【発明の詳細な説明】 (産業上の利用分野) この発明は誘電体分離基板の製造方法に係り、特に同一
基板内に異なる島深さの分離島を有する誘電体分離基板
の製造方法に関するものである.(従来の技術) 第2図(a)〜(e)は、島深さの異なる分離島を同一
基板内に有する誘電体分離基板の従来の製造方法の一例
である.この方法は特開昭63−36545号公報に開
示される. まず第2図(a)に示すように、(100)面を有する
半導体基体(単結晶シリコン基板)lの一方の主表面側
に二酸化シリコン1!2および窒化シリコン膜3からな
る2層構造被膜を形成し、かつこれをフォトリソグラフ
ィ技術によりパターニングして、深い分離島を形成する
領域にのみ2層構造被膜からなるマスク4aを形成する
.また、浅い分離島を形成する領域には、二酸化シリコ
ン膜2のみがらなるマスク4bを形成する. 次に第2図(h)に示すように水酸化カリウム水溶液を
用いて基体1をエッチングし、マスク4a,4b間に所
要深さd.の台形溝5を形成する.次に、第2図(c)
に示すように、マスク4bをバッフ1−ド弗酸(HP:
NH4F”)で除去する.この時、?スク4aは表面が
窒化シリコン膜3であるためにエッチングされることは
ない.そして、この後、水酸化カリウム水溶液で基体l
のエッチングを行い、台形溝5を同第2図(c)に示す
ようにV溝6とする.この時、基体の浅い分離島形成領
域部分7(マ゛スク4bで覆われていた部分)は、結晶
面(100)の単結晶シリコンが表面に露出しているた
め、点線から実線のように表面がd−d.だけエッチン
グされる.一方、側面は結晶面(111)であるため、
エッチング速度は極めて小さく、■溝6が形成されるこ
とになる. 次に、マスク4aを除去した後、第2図(h)に示すよ
うに、半導体基体1の前記V満6を含む主表面に二酸化
シリコン膜8を形成し、かつこの上に支持体層となる多
結晶シリコン層9をCVD法により堆積させる. その後■、半導体基体1の反対の主表面側を前記■溝6
の先端が露見するまで研磨除去することにより、第2図
{e}に示すように深い分離島lOと浅い分離島11を
有する誘電体分離基板が完成する.(発明が解決しよう
とする諜M) しかしながら、以上のような従来の方法では、第2図(
c)でV溝6を形成すると同時に浅い分離島形成領域部
分7を所望の厚さとする時に、水酸化カリウム水溶液で
のエッチングが進行するにつれて、浅い分離島形成領域
部分7の表面の結晶面(100)のみならず、該部分7
の角部に表われる(211). (311)などの高次
の結晶面がエッチングされ、しかもこれら高次の結晶面
が(111)に比べてエッチング速度が速いために、浅
い分離島形成領域部分7を所望の厚さとした時点では該
部分7の形状崩れが生じる問題点があった.そして、こ
の浅い分離島形成領域部分7の形状崩れは、すなわち浅
い分離島11の形状崩れとなり、延いてはここに形成す
る素子の特性を劣化させる問題点があった. この発明は、以上述べた浅い分離島形成領域部分を所望
の厚さにエッチングする時の該部分の形状崩れを防止し
、深い分離島と浅い分離島を形崩れなしに同一基板に形
成することができる誘電体分離基板の製造方法を提供す
ることを目的とする.(課題を解決するための手段) この発明では、半導体基体に分離用V溝形成後、該基体
の浅い分離島形成領域部分の周囲のV溝側面を酸化膜で
覆った状態で、前記浅い分離島形成領域部分の表面のエ
ッチングを行い、この浅い分離島形成領域部分を所望の
厚さとする.(作 用) 上記方法においては、■溝の側面でもある浅い分離島形
成領域部分の側面部が酸化膜で保護されるので、この浅
い分離島形成領域部分の所望厚さとするためのエッチン
グを行った時に、この浅い分離島形成領域部分の上面角
部に(111)面よりエッチング速度の速い高次の指数
を持つ面、例えば(211)面, (31.1)面が表
われず、したがって、浅い分離島形成領域部分の形状崩
れが防止される.(実施例) 以下この発明の一実施例を第1図(a)〜(h)を参照
して説明する. まず第1図(a)に示すように、(100)面を有する
?導体基体(単結晶シリコン基板)21の一方の主表面
上に、Stow膜22と、耐酸化性膜として(:VD 
SiN膜23を2層構造となるように形成する.ここで
、SIOt膜22の膜厚は、後述するアルカリ異方性エ
ッチングによるV溝形成のためのマスク材となるに充分
なだけの厚さが必要であり、例えば50nの深さのVm
を形成するには5000人程度の厚さとする。すなわち
、アルカリエッチング液として水酸化カリウム(κOH
)一イソブロビルアルコール(IPA )一水(0.0
)系を80℃で使用する場合、(100)結晶面のSi
のエッチング速度は約0. 7μ/IIIinであり、
またSiO*膜のエッチング速度は約50人/sinで
ある.深さ50Qの■溝を形成するには5 0 /0.
 7−70分要し、SiO■膜は50人×7 0 =3
500人エッチングされる.よって、マスク材としては
+αを考慮して約5000人程度必要となる.一方、C
VD SiN膜23の厚さは、アルカリ異方性エッチン
グのマスク材として数百人程度で充分である.これは、
SIN膜は前記アルカリエッチング液では殆どエッチン
グされないことによるた?である. 次に、CVD SIN III 2 3を通常のフォト
リソグラフィ技術によって一部エッチング除去して、該
CVD SiN 1g 2 3を第1図(b)に示すよ
うに浅い分離島形成領域にのみ残す.ここで、CVD 
SiN膜23は,例えばCF.+O■ガスによるドライ
エッチングにより容易に除去し得る. 次に、通常のフォトリソグラフイ技術でstoxl[l
I22とパターニングすることにより、このSi(h膜
22を第1図(c) ニ示すように前記CVO SiN
膜23の下および深い分離島形成領域に残し、■溝形成
領域部からは除去する. 次に、残存Sing膜22と残存CVD SiN膜23
をマスクとして、SiOglIi22が除去された部分
を通して基体2lをアルカリ異方性エッチングすること
により、第1図(h)に示すように分離用の■溝24を
半導体基体21に形成する. その後、露出して残存するマスクとして作用したSiO
■膜22を第1図(e)に示すように除去することによ
り、その下の基体深い分離島形成領域部分(以下第1e
JlMという)25を露出させる.そして、第1領域2
5を露出させたならば、次に第1図(f)に示すように
、CνロSiN膜23をマスクに熱酸化することで、い
わゆるLQCQS酸化II!26を第1 eM域250
表面およびV溝24側面に形成する.ここで、該LOG
OS酸化膜26の厚さは、後述するCVD SiN膜2
3とSiJ膜22のエッチング除去の際に下地の半導体
基体21をエッチングから充分に保護するとともに、後
述するアルカリ異方性エッチングのマスク材として充分
に足りる厚さであり、所望する浅い分離島厚によって決
まるが、通常は10000人程度である. 次に、そのLOCOS酸化Wa26を半導体基体2lの
保護膜として、CVD SiN膜23とstozll!
I 2 2 (7)2層を第1図(樽に示すようにエッ
チング除去し、その下の基体浅い分離島形成領域部分(
以下第2領域という)27の表面を露出させる.しかる
後、その露出表面から第1図(ハ)に示すように第2 
trl域27をアルカリ異方性エッチングし、該第2領
域27を浅い分離島として必要な厚さとする.この時、
LOCOS酸化膜26で覆われている第1 wI域25
にはエッチングの影響は全く表われない.また、■溝2
4の側面でもある第2領域27の側面が同じ< LOG
OS酸化膜26で覆われているので、第2領域27の上
面角部に(111)面よりエッチング速度の速い高次の
指数を持つ面、例えば(211)面, (311)面が
表われず、そのため第2領域27(浅い分離島)の形状
が変形することはない. しかる後、LOGOS酸化膜26を第1図(i)に示す
ように除去し、第I GW域25が再度露出した状態お
よび第2 sJi域27が完全に露出した状態とする。
Detailed Description of the Invention (Industrial Application Field) The present invention relates to a method for manufacturing a dielectrically isolated substrate, and more particularly to a method for manufacturing a dielectrically isolated substrate having isolation islands of different depths within the same substrate. It is. (Prior Art) FIGS. 2(a) to 2(e) show an example of a conventional manufacturing method of a dielectric isolation substrate having isolation islands with different island depths within the same substrate. This method is disclosed in Japanese Patent Application Laid-Open No. 63-36545. First, as shown in FIG. 2(a), a two-layer structure coating consisting of silicon dioxide 1!2 and silicon nitride film 3 is formed on one main surface side of a semiconductor substrate (single crystal silicon substrate) l having a (100) plane. is formed and patterned by photolithography to form a mask 4a consisting of a two-layer structure film only in the region where deep isolation islands are to be formed. Further, a mask 4b made only of the silicon dioxide film 2 is formed in a region where a shallow isolation island is to be formed. Next, as shown in FIG. 2(h), the substrate 1 is etched using an aqueous potassium hydroxide solution, and a required depth d. A trapezoidal groove 5 is formed. Next, Figure 2(c)
As shown in FIG.
At this time, the substrate 4a is not etched because its surface is the silicon nitride film 3. After this, the substrate 1 is removed with a potassium hydroxide aqueous solution.
The trapezoidal groove 5 is made into a V-groove 6 as shown in FIG. 2(c). At this time, in the shallow isolation island forming region portion 7 of the substrate (the portion covered by the mask 4b), the single crystal silicon of the crystal plane (100) is exposed on the surface, so the line changes from the dotted line to the solid line. The surface is dd. will be etched. On the other hand, since the side surface is a crystal plane (111),
The etching rate is extremely slow, and grooves 6 are formed. Next, after removing the mask 4a, as shown in FIG. 2(h), a silicon dioxide film 8 is formed on the main surface of the semiconductor substrate 1 including the above-mentioned V6, and a support layer is formed on this. A polycrystalline silicon layer 9 is deposited by CVD. After that, ■, the opposite main surface side of the semiconductor substrate 1 is
By polishing and removing the tip of the dielectric material until the tip thereof is exposed, a dielectric isolation substrate having a deep isolation island lO and a shallow isolation island 11 is completed as shown in FIG. 2 {e}. (Intelligence M to be solved by the invention) However, in the conventional method as described above, as shown in Fig. 2 (
When forming the V-groove 6 and at the same time forming the shallow isolation island forming region 7 in step c), as the etching with the potassium hydroxide aqueous solution progresses, the surface crystal plane of the shallow isolation island forming region 7 ( 100) as well as the part 7
(211). Higher-order crystal planes such as (311) are etched, and since these higher-order crystal planes have a faster etching rate than (111), when the shallow isolation island forming region 7 is made to the desired thickness, There was a problem that the shape of the portion 7 would be distorted. This deformation of the shallow isolation island formation region 7 leads to deformation of the shallow isolation island 11, which leads to the problem of deteriorating the characteristics of the element formed there. The present invention prevents deformation of the above-mentioned shallow isolation island forming region when etching it to a desired thickness, and forms deep isolation islands and shallow isolation islands on the same substrate without deformation. The purpose of this study is to provide a method for manufacturing dielectrically isolated substrates that can be used. (Means for Solving the Problems) In the present invention, after forming a V-groove for isolation in a semiconductor substrate, the side surface of the V-groove around a shallow isolation island forming region of the substrate is covered with an oxide film. The surface of the isolated island forming region is etched to give the shallow isolated island forming region a desired thickness. (Function) In the above method, the side surfaces of the shallow isolation island forming region, which are also the side surfaces of the trench, are protected by an oxide film, so etching is performed to obtain the desired thickness of the shallow isolation island forming region. When the etching rate is higher than that of the (111) plane, such as the (211) plane and the (31.1) plane, the plane with a higher-order index, which has a faster etching rate than the (111) plane, does not appear at the upper corner of the shallow isolation island forming region. , the deformation of the shallow isolation island forming region is prevented. (Example) An example of the present invention will be described below with reference to FIGS. 1(a) to (h). First, as shown in FIG. 1(a), does it have a (100) plane? A Stow film 22 and an oxidation-resistant film (:VD
The SiN film 23 is formed to have a two-layer structure. Here, the film thickness of the SIOt film 22 needs to be thick enough to serve as a mask material for forming a V groove by alkali anisotropic etching, which will be described later.
The thickness should be about 5,000 people to form a . That is, potassium hydroxide (κOH) was used as an alkaline etching solution.
) one isobrobyl alcohol (IPA) one water (0.0
) system at 80°C, the (100) crystal plane of Si
The etching rate is approximately 0. 7μ/IIIin,
Furthermore, the etching rate of the SiO* film is approximately 50 people/sin. To form a groove with a depth of 50Q, use 50/0.
It takes 7-70 minutes, and the SiO film requires 50 people x 70 = 3
500 people are etched. Therefore, approximately 5,000 people will need mask materials, taking into account +α. On the other hand, C
The thickness of the VD SiN film 23 of several hundred is sufficient as a mask material for alkaline anisotropic etching. this is,
Is this because the SIN film is hardly etched with the alkaline etching solution? It is. Next, a portion of the CVD SiN III 2 3 is removed by ordinary photolithography, leaving the CVD SiN 1g 2 3 only in the shallow isolation island forming region as shown in FIG. 1(b). Here, CVD
The SiN film 23 is made of, for example, CF. It can be easily removed by dry etching using +O■ gas. Next, stoxl [l
By patterning with I22, this Si(h film 22 is formed into the CVO SiN film 22 as shown in FIG. 1(c)).
It is left under the film 23 and in the deep separation island formation region, and is removed from the groove formation region. Next, the remaining Sing film 22 and the remaining CVD SiN film 23
Using as a mask, the substrate 2l is subjected to alkali anisotropic etching through the portion where the SiOglIi 22 has been removed, thereby forming a groove 24 for isolation in the semiconductor substrate 21, as shown in FIG. 1(h). Afterwards, the exposed SiO remained as a mask.
(1) By removing the film 22 as shown in FIG.
25 (called JlM) is exposed. And the first area 2
5 is exposed, next, as shown in FIG. 1(f), thermal oxidation is performed using the Cν SiN film 23 as a mask, resulting in so-called LQCQS oxidation II! 26 to 1st eM area 250
Formed on the surface and the sides of the V-groove 24. Here, the LOG
The thickness of the OS oxide film 26 is the same as that of the CVD SiN film 2, which will be described later.
3 and the SiJ film 22 are sufficiently protected from etching when the SiJ film 22 is removed, and the thickness is sufficient as a mask material for the alkali anisotropic etching described later, and the thickness is sufficient to achieve the desired shallow isolation island thickness. It depends on the number of people, but usually it is around 10,000 people. Next, using the LOCOS oxidized Wa 26 as a protective film for the semiconductor substrate 2l, the CVD SiN film 23 and stozll!
I 2 2 (7) The two layers are removed by etching as shown in Figure 1 (barrel), and the shallow isolation island forming region of the substrate below (
27 (hereinafter referred to as the second region) is exposed. After that, from the exposed surface, as shown in FIG.
The trl region 27 is anisotropically etched with alkali to form the second region 27 into a shallow isolation island with a required thickness. At this time,
First wI region 25 covered with LOCOS oxide film 26
The effect of etching does not appear at all. Also, ■Groove 2
The side surface of the second area 27, which is also the side surface of 4, is the same < LOG
Since the second region 27 is covered with the OS oxide film 26, a plane with a higher-order index having a faster etching rate than the (111) plane, such as a (211) plane and a (311) plane, appears at the upper corner of the second region 27. Therefore, the shape of the second region 27 (shallow isolated island) will not be deformed. Thereafter, the LOGOS oxide film 26 is removed as shown in FIG. 1(i), leaving the IGW region 25 exposed again and the second sJi region 27 completely exposed.

その後は通常の誘電体分離基板の製造方法にのっとって
、まず第1図0)に示すように第I Si域25と第2
領域27の全面の表層部分に埋込層28を形成する.次
に同図のように、第1領域25と第2領域27の全面に
分離酸化膜29を連続的に形成し、その上に支持体層と
して厚い多結晶シリコン層30を堆積させる.その後、
半導体基体2lのもう一方の主表面側を前記■溝24の
先端が露見するまで研磨除去して、第1図(9)に示す
ように第1領域25と第2 fill域27を深い分離
島25aと浅い分離島27aとして完全に分離させるこ
とにより、これら深さの異なる分離島を同一基板内に有
する誘電体分a基板を完成させる.(発明の効果) 以上詳細に説明したように、この発明の製造方法によれ
ば、基体の浅い分離島形成領域部分の側面部を酸化膜で
保護した状態で、該領域部分を所望の・厚さとするため
のエッチングを行うようにしたので、該エッチング時、
前記領域部分の角部にエッチング速度の速い高次の指数
を持つ面が表われることを防止でき、前記領域部分の変
形ひいては浅い分離島の変形を防止できる.よって、こ
の浅い分離島に形成される素子の特性を向上させること
が可能となる.
After that, in accordance with the usual manufacturing method of a dielectric isolation substrate, the first Si region 25 and the second
A buried layer 28 is formed in the surface layer portion of the entire surface of the region 27. Next, as shown in the figure, an isolation oxide film 29 is continuously formed over the entire surface of the first region 25 and second region 27, and a thick polycrystalline silicon layer 30 is deposited thereon as a support layer. after that,
The other main surface side of the semiconductor substrate 2l is polished away until the tips of the grooves 24 are exposed, and the first region 25 and the second fill region 27 are formed into deep isolation islands as shown in FIG. 1(9). By completely separating the isolation islands 25a and 27a, a dielectric substrate having isolation islands of different depths on the same substrate is completed. (Effects of the Invention) As described in detail above, according to the manufacturing method of the present invention, the shallow isolation island forming region of the base body is coated with a desired thickness while the side surface of the shallow isolation island forming region is protected with an oxide film. Since we performed etching to improve the
It is possible to prevent a surface having a high etching rate and a high-order index from appearing at the corner of the region, and it is possible to prevent deformation of the region and, by extension, deformation of the shallow isolated island. Therefore, it is possible to improve the characteristics of elements formed on this shallow isolation island.

【図面の簡単な説明】[Brief explanation of the drawing]

Claims (1)

【特許請求の範囲】 (a)半導体基体の一方の主表面上に酸化膜を形成し、
その上に耐酸化性膜を形成する工程と、(2)その耐酸
化性膜をパターニングして該耐酸化性膜を浅い分離島形
成領域にのみ残す工程と、(c)その後、前記酸化膜を
パターニングして、この酸化膜を前記耐酸化性膜の下と
深い分離島形成領域に残し、V溝形成部分からは除去す
る工程と、(d)その酸化膜が除去された部分を通して
前記半導体基体をエッチングし、該基体に分離用V溝を
形成する工程と、 (e)その後、深い分離島形成領域に露出して残存する
前記酸化膜を除去し、その下の基体深い分離島形成領域
部分の表面を露出させる工程と、(f)その露出した基
体深い分離島形成領域部分の表面およびV溝側面に保護
膜およびマスク材としての酸化膜を形成する工程と、 (g)その後、浅い分離島形成領域に残存する耐酸化性
膜とその下の酸化膜を除去し、その下の基体浅い分離島
形成領域部分の表面を露出させる工程と、 (h)その基体浅い分離島形成領域部分を前記保護膜お
よびマスク材としての酸化膜をマスクとして所望の厚さ
までエッチング除去する工程と、(i)その後、前記保
護膜およびマスク材としての酸化膜を除去した後、それ
により露出した基体深い分離島形成領域部分の全面およ
び所望の厚さとなって露出する基体浅い分離島形成領域
部分の全面に分離絶縁膜を連続して形成し、その上に支
持体層を堆積させる工程と、 (j)その後、半導体基体の他方の主表面側から該基体
をV溝先端が露見するまで除去する工程とを具備してな
る誘電体分離基板の製造方法。
[Claims] (a) forming an oxide film on one main surface of a semiconductor substrate;
a step of forming an oxidation-resistant film thereon; (2) a step of patterning the oxidation-resistant film to leave the oxidation-resistant film only in the shallow isolation island formation region; (d) patterning the oxide film, leaving this oxide film under the oxidation-resistant film and in the deep isolation island formation region, and removing it from the V-groove formation area; (d) patterning the oxide film through the removed part; a step of etching the substrate to form an isolation V-groove in the substrate; (e) then removing the oxide film exposed and remaining in the deep isolation island formation region, and etching the deep isolation island formation region of the substrate below; (f) forming an oxide film as a protective film and mask material on the exposed surface of the deep isolation island forming region of the substrate and on the side surfaces of the V-groove; (g) then forming a shallow (h) removing the oxidation-resistant film remaining in the isolation island formation region and the oxide film thereunder, and exposing the surface of the shallow isolation island formation region portion of the substrate underneath; (h) the shallow isolation island formation region portion of the substrate; (i) Then, after removing the protective film and the oxide film as a mask material, the exposed substrate is removed by etching to a desired thickness using the protective film and the oxide film as a mask material as a mask; a step of continuously forming an isolation insulating film on the entire surface of the isolation island forming region and the entire surface of the shallow isolation island forming region of the substrate exposed to a desired thickness, and depositing a support layer thereon; ) Thereafter, the substrate is removed from the other main surface side of the semiconductor substrate until the tip of the V-groove is exposed.
JP11508389A 1989-05-10 1989-05-10 Manufacturing method of dielectric isolation substrate Expired - Fee Related JP2667708B2 (en)

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Application Number Priority Date Filing Date Title
JP11508389A JP2667708B2 (en) 1989-05-10 1989-05-10 Manufacturing method of dielectric isolation substrate

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JPH02295151A true JPH02295151A (en) 1990-12-06
JP2667708B2 JP2667708B2 (en) 1997-10-27

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03245552A (en) * 1990-02-23 1991-11-01 Matsushita Electric Works Ltd Manufacture of insulating layer isolated board material

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03245552A (en) * 1990-02-23 1991-11-01 Matsushita Electric Works Ltd Manufacture of insulating layer isolated board material

Also Published As

Publication number Publication date
JP2667708B2 (en) 1997-10-27

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