JPS6336545A - Manufacture of dielectric isolation type semiconductor device - Google Patents

Manufacture of dielectric isolation type semiconductor device

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Publication number
JPS6336545A
JPS6336545A JP17883586A JP17883586A JPS6336545A JP S6336545 A JPS6336545 A JP S6336545A JP 17883586 A JP17883586 A JP 17883586A JP 17883586 A JP17883586 A JP 17883586A JP S6336545 A JPS6336545 A JP S6336545A
Authority
JP
Japan
Prior art keywords
etching
single crystal
crystal silicon
island
masks
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17883586A
Other languages
Japanese (ja)
Inventor
Masahide Miwa
三輪 正英
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP17883586A priority Critical patent/JPS6336545A/en
Publication of JPS6336545A publication Critical patent/JPS6336545A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To make it possible to form excellent island regions and to improve the integration degree and the characteristics of an element, in etching for forming the island regions having different depths, by using masks, in which two or more kinds of etching resisting films are combined, thereby improving the manufacturing yield rate and accuracy. CONSTITUTION:Masks 7a and 7b are selectively formed on the surface of a single crystal semiconductor substrate 1. The semiconductor substrate 1 is partially etched in different depths by using the masks 7a and 7b. A dielectric isolation film 4 and a supporting body layer 5 are deposited on the surface. Thereafter, the rear surface of the semiconductor substrate 1 is polished, and first and second single crystal semiconductor islands 6a and 6b, which are insulated and isolated from each other and have different depths, are formed. When the dielectric isolation type semiconductor device is manufactured in this way, the masks 7a and 7b, which are used in said etching, have the structure, in which two or more kinds of etching resisting films 2 and 3 are made to correspond to the island regions in different combinations. The process, in which the single crystal silicon substrate 1 is selectively etched by using the masks 7a and 7b, and a process, in which the etching resisting films 2 and 3 of the masks are sequentially removed, are laternately performed.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に関し、特に絶縁分離型
半導体装置の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing an isolation type semiconductor device.

゛〔従来の技術〕 従来、絶縁分離型半導体装置は、第4図(a)。゛ [Conventional technology] A conventional isolation type semiconductor device is shown in FIG. 4(a).

(b)に示すように、多結晶シリコン等の支持体層5と
、二酸化シリコン膜等の絶縁分離膜4と、絶縁分離膜で
包まれた単結晶シリコン島6とで構成されている。そし
て、単結晶シリコン島6の深さにより、例えば特公昭4
1−160707号に開示されている同図(a>のよう
な均一な深さの単結晶シリコン島6aのみを備えるもの
や、例えば特開昭57−59350号に開示されている
同図(b)のような異なる深さの単結晶シリコン島5a
、5bを備えるものとが提案されている。
As shown in (b), it is composed of a support layer 5 made of polycrystalline silicon or the like, an insulating separation film 4 such as a silicon dioxide film, and a single crystal silicon island 6 wrapped in the insulating separation film. Depending on the depth of the single crystal silicon island 6, for example,
1-160707, which has only a monocrystalline silicon island 6a with a uniform depth, or the one shown in FIG. ) with different depths of monocrystalline silicon islands 5a.
, 5b has been proposed.

これらの構造の中、特に後者の島構造では、高耐圧素子
や低耐圧素子が混在する集積回路装置の製造に際して、
低耐圧素子の特性向上や集積度の向上を図る上で有効で
ある。
Among these structures, especially the latter island structure, when manufacturing integrated circuit devices in which high-voltage elements and low-voltage elements coexist,
This is effective in improving the characteristics of low voltage elements and increasing the degree of integration.

第5図(a)〜(e)はこの後者の島構造を製造する方
法を示しており、ここでは島深さhlの第1単結晶シリ
コン島6aとこれよりも深さhlが小さい第2単結晶シ
リコン島6bを形成する工程を示している。
FIGS. 5(a) to 5(e) show a method for manufacturing this latter island structure, in which a first single-crystal silicon island 6a with an island depth hl and a second single-crystal silicon island 6a with a smaller depth hl are shown in FIGS. It shows the process of forming a single crystal silicon island 6b.

先ず、同図(a)のように、単結晶シリコン基板1の表
面に熱酸化法により耐アルカリ製被膜として二酸化シリ
コン膜2を形成する。次いで第1回目のフォトリソグラ
フィ工程を行い、第2単結晶シリコン島形成領域の二酸
化シリコン膜2に開口寸法W0を有するマスク開口窓8
を形成する。
First, as shown in FIG. 2A, a silicon dioxide film 2 is formed as an alkali-resistant coating on the surface of a single-crystal silicon substrate 1 by thermal oxidation. Next, a first photolithography process is performed to form a mask opening window 8 having an opening size W0 in the silicon dioxide film 2 in the second single crystal silicon island formation region.
form.

そして、水酸化カリウム水溶液による異方性エツチング
により、単結晶シリコン基板1に深さdoの窪み部9a
を形成する。
Then, by anisotropic etching with an aqueous potassium hydroxide solution, a recess 9a having a depth of do is formed in the single crystal silicon substrate 1.
form.

次いで、同図(b)のように単結晶シリコン基板1の全
面に二酸化シリコン膜2Aを形成し、第2回目のフォト
リソグラフィ工程を行って第1単結晶シリコン島6a形
成領域及び第2単結晶シリコン島6b形成領域に夫々開
口寸法W、、W2の開口窓8a、8bを開設する。この
場合、島深さり、>h、であれば開口寸法もW、>W2
に設定する。
Next, a silicon dioxide film 2A is formed on the entire surface of the single crystal silicon substrate 1 as shown in FIG. Opening windows 8a and 8b having opening dimensions W, . . . W2 are opened in the silicon island 6b formation region, respectively. In this case, if the island depth is >h, the opening size is also W, >W2
Set to .

その後、同図(C)のように前記二酸化シリコン膜2A
をマスクにし、第1単結晶シリコン島6−aを形成する
に必要な深さd、まで単結晶シリコン基板1を異方性エ
ツチングし、VilOaを形成する。このとき、W=2
””xdの関係から、第2単結晶シリコン島6bの形成
領域では、開口寸法W2に従って深さd2のV#10b
が形成される。
After that, as shown in the same figure (C), the silicon dioxide film 2A
Using this as a mask, the single crystal silicon substrate 1 is anisotropically etched to a depth d required to form the first single crystal silicon island 6-a, thereby forming VilOa. At this time, W=2
From the relationship of xd, in the formation region of the second single crystal silicon island 6b, V#10b of depth d2 according to the opening dimension W2.
is formed.

更に、同図(d)のように二酸化シリコン膜2Aを除去
した後、全面に絶縁分離膜4として二酸化シリコン膜を
約2μmの厚さに形成し、この上に支持体層5として多
結晶シリコン5をCVD法により所要厚さに形成する。
Furthermore, after removing the silicon dioxide film 2A as shown in FIG. 4(d), a silicon dioxide film with a thickness of about 2 μm is formed as an insulating separation film 4 on the entire surface, and a polycrystalline silicon film is formed on this as a support layer 5. 5 is formed to a required thickness by CVD method.

その後、単結晶シリコン基板側を裏面側から絶縁分離膜
4の一部が露呈されるまで研磨することにより、同図(
e)のように深さの異なる第1及び第2の単結晶シリコ
ン島6a、6bが完成される。
Thereafter, the single-crystal silicon substrate side is polished from the back side until a part of the insulating separation film 4 is exposed, as shown in the same figure.
First and second single crystal silicon islands 6a and 6b having different depths are completed as shown in e).

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来の製造方法では、次のような問題が生じて
いる。
The conventional manufacturing method described above has the following problems.

(1)第2回目のフォトリソグラフィ工程では、窪み部
9aが形成された単結晶シリコン基板1を取り扱うため
に、基板が割れ易く、歩留低下を起こし易い。
(1) In the second photolithography step, since the single crystal silicon substrate 1 with the recessed portion 9a is handled, the substrate is likely to be broken, resulting in a decrease in yield.

(2)窪み部9aが形成されて凹凸の大きい基板1の表
面に第2回目のフォトリソグラフィ工程を行うことにな
るため、精度の低下を招く。
(2) Since the second photolithography process is performed on the surface of the substrate 1 which has large irregularities due to the formation of the recessed portion 9a, the accuracy is lowered.

(3)第2回目の異方性エツチングでは、島深さの大き
いV溝10aを形成するためのエツチング時間が必要と
されるため、浅いV溝10bが余分にエツチングされ、
ここに形成する島形状が崩れて素子の特性劣化を招き易
い。
(3) In the second anisotropic etching, etching time is required to form the V-groove 10a with a large island depth, so the shallow V-groove 10b is etched extra.
The island shape formed here is likely to collapse, resulting in deterioration of the characteristics of the element.

(4)公知の異方性エツチングのマスク設計方法(例え
ば、特公昭45−17988号)からシリコン単結晶島
形状を均一に形成するため、マスクの角部に補償パター
ンをイイ加する必要性が知られているが、窪み部9aの
境界部分での補償パターンの最適化が重要となり、設計
の難しさを伴う。
(4) From the known anisotropic etching mask design method (for example, Japanese Patent Publication No. 45-17988), it is necessary to add a compensation pattern to the corners of the mask in order to uniformly form a silicon single crystal island shape. Although this is known, it is important to optimize the compensation pattern at the boundary portion of the recessed portion 9a, which is accompanied by difficulty in design.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の絶縁分離型半導体装置の製造方法は、以上の問
題に鑑み、製造歩留及び精度の向上を図−って良好な島
領域を形成可能にするとともに、ここに形成する素子の
集積度及び特性の向上を可能とし、更に設計の容易化を
可能とするものである。
In view of the above-mentioned problems, the method of manufacturing an isolation type semiconductor device of the present invention aims to improve manufacturing yield and precision, makes it possible to form a good island region, and improves the integration of elements formed here. This makes it possible to improve the characteristics and the characteristics, and also to facilitate the design.

本発明の絶縁分離型半導体装置の製造方法は、各界なる
深さの島領域を形成するための単結晶半導体基板のエツ
チングに際し、エツチングに用いるマスクを2種類以上
の耐エツチング被膜を各島領域に対応させて異なる組合
わせの構造とし、これらマスクを用いて単結晶シリコン
基板を選択エツチングする工程と、これらマスクの耐エ
ツチング被膜を上層から順次除去する工程とを交互に行
うことを特徴とするものである。
In the method of manufacturing an isolation type semiconductor device of the present invention, when etching a single crystal semiconductor substrate to form island regions of various depths, two or more types of etching-resistant coatings are applied to each island region using a mask used for etching. The method is characterized in that the structures have different combinations in correspondence with each other, and the step of selectively etching a single crystal silicon substrate using these masks and the step of sequentially removing the etching-resistant coating of these masks from the upper layer are performed alternately. It is.

〔実施例〕〔Example〕

次に、本発明を図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

(実施例工) 第1図(a)〜(e)は本発明の第1実施例を製造工程
順に示す断面図であり、ここでは深さhlの第1単結晶
シリコン島6aと、深さhzの第2単結晶シリコン島5
b (h+  >h、)とからなる2種類の深さの単結
晶シリコン島を形成する例を示している。
(Example Work) FIGS. 1(a) to 1(e) are cross-sectional views showing the first embodiment of the present invention in the order of manufacturing steps, and here, a first single crystal silicon island 6a with a depth hl and a first single crystal silicon island 6a with a depth hl, hz second single crystal silicon island 5
b shows an example of forming single-crystal silicon islands with two different depths, where h+ >h,).

先ず、同図(a)のように結晶面(100)の単結晶シ
リコン基板1の表面に、後述する厚さの二酸化シリコン
膜2及び窒化シリコン膜3からなる二層構造被膜を形成
しかつこれをフォトリソグラフィ技術によりバターニン
グし、第1の単結晶シリコン島6aに相当する領域にの
み二層構造被膜からなるマスク7aを形成する。また、
第2の単結晶シリコン島6bに相当する領域には、二酸
化シリコン膜2のみからなるマスク7bを形成する。
First, as shown in FIG. 2(a), a two-layer structure film consisting of a silicon dioxide film 2 and a silicon nitride film 3 having a thickness to be described later is formed on the surface of a single crystal silicon substrate 1 with a crystal plane (100). is patterned by photolithography, and a mask 7a consisting of a two-layer structure film is formed only in the region corresponding to the first single crystal silicon island 6a. Also,
A mask 7b made of only silicon dioxide film 2 is formed in a region corresponding to second single-crystal silicon island 6b.

このとき、マスクにおける開口8の寸法Wは第1単結晶
シリコン島6aを形成するに必要な幅とし、島深さhl
に後工程での研磨バラツキ(Δh)を考慮したエツチン
グ深さd=h、  +Δhから決める。
At this time, the dimension W of the opening 8 in the mask is the width necessary to form the first single-crystal silicon island 6a, and the island depth hl
The etching depth is determined from d=h, +Δh, taking into consideration the polishing variation (Δh) in the subsequent process.

次いで、同図(b)のように、水酸化カリウム水溶液を
用いて単結晶シリコン基板1をエツチングし、所要深さ
doの台形溝9を形成する。
Next, as shown in FIG. 4B, the single crystal silicon substrate 1 is etched using an aqueous potassium hydroxide solution to form a trapezoidal groove 9 of a required depth do.

次に、同図(C)のように第2単結晶シリコン′島6b
jI域におけるマスク7bとしての二酸化シリコン膜2
を二酸化シリコン膜エツチング液、例えばバンファード
弗酸(HF : NH4F)で除去する。なお、第1単
結晶シリコン島63領域のマスク7aは表面が窒化シリ
コン膜3であるために、エツチングされることはない。
Next, as shown in the same figure (C), the second single crystal silicon island 6b
Silicon dioxide film 2 as mask 7b in jI region
The silicon dioxide film is removed using a silicon dioxide film etching solution such as Banfurd hydrofluoric acid (HF: NH4F). Note that since the surface of the mask 7a in the first single crystal silicon island 63 region is the silicon nitride film 3, it is not etched.

そして、水酸化カリウム水溶液でエツチングを行い、■
溝10を形成する。
Then, etching is performed with an aqueous potassium hydroxide solution, and ■
A groove 10 is formed.

このとき、第2単結晶シリコン島5beN域の表面は結
晶面(100)の単結晶シリコンが露出しているため、
点線のように基板表面がd−doだけエツチングされる
ことになる。一方、側面は結晶面(111)であるため
、エツチング速度が極めて遅く、■溝10が形成される
ことになる。
At this time, since the surface of the second single crystal silicon island 5beN region has exposed single crystal silicon in the crystal plane (100),
The substrate surface is etched by d-do as shown by the dotted line. On the other hand, since the side surfaces are crystal planes (111), the etching rate is extremely slow, resulting in the formation of grooves 10.

次いで、同図(d)のように、基板1の表面に絶縁分離
膜として二酸化シリコン膜4を形成し、かつこの上に支
持体層とて多結晶シリコン5をCVD法により堆積させ
る。このとき、埋込層を形成する場合には、絶縁分離膜
4の形成する前に熱拡散やイオン注入法等によって不純
物を4人しておくことは言うまでもない。
Next, as shown in FIG. 1D, a silicon dioxide film 4 is formed as an insulating separation film on the surface of the substrate 1, and polycrystalline silicon 5 is deposited thereon as a support layer by CVD. At this time, when forming a buried layer, it goes without saying that four impurities are added by thermal diffusion, ion implantation, etc. before forming the insulating separation film 4.

その後、単結晶シリコン基板1を裏面側から研摩して絶
縁分離膜4の一部を露呈させることにより、同図(e)
のように第1及び第2の単結晶シリコン島6a、6bを
完成する。
Thereafter, the single crystal silicon substrate 1 is polished from the back side to expose a part of the insulating separation film 4, as shown in FIG.
First and second single crystal silicon islands 6a and 6b are completed as shown in FIG.

ここで、例えば、第1単結晶シリコン島6aの深さh+
=45μm、第2単結晶シリコン島6bの深さhz ”
 20μm、研磨バラツキΔh=5μmとした場合、所
望エツチング深さd#h、  +Δh=50crm、d
o =25pmとなり、マスク開口寸法W = 21/
2 X d″−10μmとなる。
Here, for example, the depth h+ of the first single crystal silicon island 6a
=45 μm, depth hz of second single crystal silicon island 6b”
20 μm, polishing variation Δh=5 μm, desired etching depth d#h, +Δh=50 crm, d
o = 25pm, mask opening size W = 21/
2×d″−10 μm.

また、水酸化カリウム水溶液を80℃でエツチングする
場合には、単結晶シリコン基板1の結晶面(100)の
エツチング速度は約1μm/分。
Further, when etching a potassium hydroxide aqueous solution at 80° C., the etching rate of the crystal plane (100) of the single crystal silicon substrate 1 is about 1 μm/min.

二酸化シリコン膜2のエツチング速度は約50人/分、
窒化シリコン膜3のエツチング速度は約5人/分である
。したがって、所望深さd=50μmを得るためのエツ
チング時間は約50分であり、また各二酸化シリコン膜
2及び窒化シリコン膜3の[は夫々1250人、250
人にすればよい。
The etching speed of the silicon dioxide film 2 is approximately 50 people/min.
The etching rate of the silicon nitride film 3 is about 5 people/min. Therefore, the etching time to obtain the desired depth d=50 μm is about 50 minutes, and the etching time for each silicon dioxide film 2 and silicon nitride film 3 is 1250 and 250, respectively.
Just do it to a person.

−この方法によれば、マスク7a、7bとしての二酸化
シリコン膜2や窒化シリコン膜3を形成するためのフォ
トリソグラフィ工程は平坦な単結晶シリコン基板1の状
態で行っているため、割れ等が生じることはなく、しか
も高精度にできるので歩留を向上できる。また、これら
マスク7a、7bの構成により2種類の深さの島6a、
6bを同時にエツチング形成できるので、形状の崩れの
ない島領域を形成し、集積度の向上及び素子特性の向上
を図ることができる。
- According to this method, the photolithography process for forming the silicon dioxide film 2 and the silicon nitride film 3 as the masks 7a and 7b is performed on the flat single crystal silicon substrate 1, which causes cracks, etc. Moreover, since it can be done with high precision, the yield can be improved. Also, depending on the configuration of these masks 7a and 7b, two types of depths of islands 6a,
Since 6b can be etched at the same time, it is possible to form an island region whose shape does not collapse, thereby improving the degree of integration and device characteristics.

ここで、第1車結晶シリコン島6aのマスクには窒化シ
リコン膜の単層膜を用いてもよい。また、第1及び第2
単結晶シリコン膜のマスク構成を逆の関係にして形成す
ることもできる。
Here, a single layer film of silicon nitride film may be used as a mask for the first wheel crystal silicon island 6a. Also, the first and second
It is also possible to form the single crystal silicon film with the mask configuration reversed.

(実施例2) 第2図(a)〜(e)は本発明の第2実施例を製造工程
順に示す断面図であり、ここでは第1乃至第3の異なる
深さり、、hz 、hz  (h+  >hz〉h3)
の単結晶シリコン島6a〜6cを形成する例を示してい
る。
(Example 2) FIGS. 2(a) to 2(e) are cross-sectional views showing a second example of the present invention in the order of manufacturing steps, and here, the first to third different depths, hz, hz ( h+ >hz>h3)
An example of forming single crystal silicon islands 6a to 6c is shown.

先ず、同図(a)のように結晶面(100)の単結晶シ
リコン基板1の表面の第1単結晶シリコン島6 a f
il域の表面に二酸化シリコン膜2.窒化シリコン膜3
.二酸化シリコン膜2からなる三層構造被膜のマスク7
aを、第2単結晶シリコン島6bjl域の表面には窒化
シリコン膜3及び二酸化シリコン膜2からなる二層構造
被膜のマスク7bを、更に第3単結晶シリコン島6c8
M域の表面には二酸化シリコン膜2のみのマスク7cを
夫々フォトリソグラフィ工程により順次形成する。この
とき、最小マスク開口8の寸法Wは、前記第1実施例と
同様に、必要エツチング深さd=h、 十Δhから求め
ることができる。
First, as shown in FIG. 6(a), a first single crystal silicon island 6 a f is formed on the surface of a single crystal silicon substrate 1 having a crystal plane (100).
Silicon dioxide film 2 on the surface of the il region. Silicon nitride film 3
.. Mask 7 with a three-layer structure film consisting of silicon dioxide film 2
a, a mask 7b having a two-layer structure consisting of a silicon nitride film 3 and a silicon dioxide film 2 is provided on the surface of the second single-crystal silicon island 6bjl region, and a third single-crystal silicon island 6c8
Masks 7c made of only silicon dioxide film 2 are sequentially formed on the surface of region M by a photolithography process. At this time, the dimension W of the minimum mask opening 8 can be determined from the required etching depth d=h and Δh, as in the first embodiment.

次に、同図(b)のように水酸化カリウム水溶液により
、所望深さdoだけ基板1のエツチングを行ない、台形
溝9を形成する。このエツチング深さは第3単結晶シリ
コン島6cの深さによって決定される。
Next, as shown in FIG. 2B, the substrate 1 is etched to a desired depth do using a potassium hydroxide aqueous solution to form a trapezoidal groove 9. This etching depth is determined by the depth of the third single crystal silicon island 6c.

次いで、同図(c)のように第3単結晶シリコン、%6
c6J[[表面のマスク7cの二酸化シリコン°膜2を
バッフアート弗酸でエツチング除去する。
Next, as shown in the same figure (c), third single crystal silicon, %6
c6J[[The silicon dioxide film 2 of the mask 7c on the surface is removed by etching with buffered hydrofluoric acid.

このとき、第1及び第2単結晶シリコン島6a。At this time, the first and second single crystal silicon islands 6a.

6bSN域のマスク?a、7bの表面は窒化シリコン膜
3が夫々設けられているのでマスクが除去されることは
ない。そして、この状態で水酸化カリウム水溶液で台形
溝9のエツチングを深さd、まで進めると、第3単結晶
シリコン島60領域の表面はエツチングが進み、図示点
線のように単結晶シリコン島の底面部がd、−doだけ
浅くなる。
6bSN area mask? Since the silicon nitride film 3 is provided on the surfaces of a and 7b, the mask is not removed. In this state, when the etching of the trapezoidal groove 9 is progressed to a depth d using an aqueous potassium hydroxide solution, the etching progresses on the surface of the third single crystal silicon island 60 region, and the bottom surface of the single crystal silicon island is shown as a dotted line in the figure. The part becomes shallower by d, -do.

次に、同図(d)のように第2単結晶シリコン島6b領
域表面の窒化シリコン膜3をリン酸(H3P04)でエ
ツチング除去する。このとき、第1単結晶シリコン島6
a領域の表面では二酸化シリコン膜2がマスクとして残
される。そして、水酸化カリウム水溶液で深さdまでエ
ツチングを進めて■溝10を形成すると、第2及び第3
単結晶シリコン島5b、5c領域の表面は、図示鎖線の
ようにd−d、たけエツチングされる。これにより、第
2単結晶シリコン島6b領域はd−d、に、また第3単
結晶シリコン島6c’6TI域はd−doの位置まで夫
々底面部が浅くなる。
Next, as shown in FIG. 4(d), the silicon nitride film 3 on the surface of the second single crystal silicon island 6b region is removed by etching with phosphoric acid (H3P04). At this time, the first single crystal silicon island 6
The silicon dioxide film 2 is left as a mask on the surface of region a. Then, etching is performed to a depth d using a potassium hydroxide aqueous solution to form the grooves 10.
The surfaces of the single-crystal silicon islands 5b and 5c are etched by a depth dd as shown by the chain line in the figure. As a result, the bottom surface of the second single crystal silicon island 6b region becomes shallow to the position dd, and the bottom surface of the third single crystal silicon island 6c'6TI region becomes shallow to the position d-do.

以下、第1実施例と同様に絶縁分離膜として二酸化シリ
コン膜4を形成し、かつ支持体層として多結晶シリコン
5を堆積し、少なくとも単結晶シリコン基板1を研磨す
ることにより、同図(e)のように3種類の異なる深さ
の第1〜第3の単結晶シリコン島6a〜6cを完成でき
る。
Thereafter, as in the first embodiment, a silicon dioxide film 4 is formed as an insulating separation film, a polycrystalline silicon 5 is deposited as a support layer, and at least the single crystal silicon substrate 1 is polished. ), the first to third single crystal silicon islands 6a to 6c having three different depths can be completed.

第3図は、このようにして形成された単結晶シリコン島
内に、半導体素子を形成した例を示す。
FIG. 3 shows an example in which a semiconductor element is formed within the single crystal silicon island thus formed.

単結晶シリコン島の深さに対応して夫々高耐圧素子、中
耐圧素子、低耐圧素子を容易に形成できる。
High-voltage elements, medium-voltage elements, and low-voltage elements can be easily formed depending on the depth of the single-crystal silicon island.

ここでは、島6aにサイリスタ11を、島6bにNPN
バイポーラトランジスタ12を、島6cにMOS)ラン
ジスタ13を形成している。図において、14は絶縁膜
、15は金属配線層、16は各種拡散層である。
Here, the thyristor 11 is installed on the island 6a, and the NPN is installed on the island 6b.
A bipolar transistor 12 is formed on the island 6c, and a MOS transistor 13 is formed on the island 6c. In the figure, 14 is an insulating film, 15 is a metal wiring layer, and 16 is various diffusion layers.

この実施例においても、前記第1実施例と同様の効果を
得ることができる。
In this embodiment as well, the same effects as in the first embodiment can be obtained.

なお、単結晶シリコン島形成領域のマスクとして、第1
単結晶シリコン島6aには二酸化シリコ゛ ン膜と窒化
シリコン膜からなる二層構造の被膜を、第2単結晶シリ
コン島6bには窒化シリコン膜のみの被膜を、第3単結
晶シリコン島6cには二酸化シリコン膜のみの被膜を夫
々マスクとして構成しても同様に形成を行うことができ
る。この場合、二酸化シリコン膜と窒化シリコン膜に限
らず、2種類以上の耐アルカリ性被膜の組合わせであれ
ば、他の被膜を用いることができるのは言うまでもない
Note that the first mask is used as a mask for the single-crystal silicon island formation region.
The single-crystal silicon island 6a is coated with a two-layer structure consisting of a silicon dioxide film and a silicon nitride film, the second single-crystal silicon island 6b is coated with only a silicon nitride film, and the third single-crystal silicon island 6c is coated with a film of only a silicon nitride film. Formation can be performed in the same manner even if a film made of only a silicon dioxide film is used as a mask. In this case, it goes without saying that the silicon dioxide film and the silicon nitride film are not limited, but other films can be used as long as they are a combination of two or more types of alkali-resistant films.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、各界なる深さの島領域を
形成するための単結晶半導体基板のエツチングに際し、
エツチングに用いるマスクを2種類以上の耐エツチング
被膜を各島領域に対応させて異なる組合わせの構造とし
、これらマスクを用いて単結晶シリコン基板を選択エツ
チングする工程と、これらマスクの耐エツチング被膜を
上層から順次除去する工程とを交互に行うことを特徴と
しているので、次の効果を得ることができる。
As explained above, the present invention enables etching of a single crystal semiconductor substrate to form island regions of various depths.
The mask used for etching has a structure with different combinations of two or more types of etching-resistant coatings corresponding to each island region, and the process of selectively etching a single crystal silicon substrate using these masks, and the etching-resistant coating of these masks. Since the method is characterized in that the steps of sequentially removing the upper layer are performed alternately, the following effects can be obtained.

(1)平坦な単結晶シリコン基板に対してフォトリソグ
ラフィ工程を施すので、強度が低下して工程中に割れ等
が生じることはなく、また高精度に製造できるので歩留
を向上することができる。
(1) Since the photolithography process is performed on a flat single-crystal silicon substrate, there will be no decrease in strength or cracks during the process, and high-precision manufacturing can improve yields. .

(2)耐アルカリ性膜の組合わせでマスクを形成してい
るので、2種類以上の深さの単結晶シリコン島を同時エ
ツチングにより形成でき、かつ半導体素子の要求特性に
合わせて島深さを設定できるので集積度の向上を図るこ
とができる。
(2) Since the mask is formed by a combination of alkali-resistant films, single-crystal silicon islands with two or more depths can be formed by simultaneous etching, and the island depth can be set according to the required characteristics of the semiconductor element. Therefore, it is possible to improve the degree of integration.

(3)2種類以上の深さの単結晶シリコン島を同時エツ
チングにより形成できるので、各単結晶シリコン島の形
状筋れが生じることは少なく、ここに形成する素子の特
性が劣化されることはない。
(3) Since single-crystal silicon islands with two or more depths can be formed by simultaneous etching, the shape of each single-crystal silicon island is less likely to be distorted, and the characteristics of the elements formed here are less likely to deteriorate. do not have.

(4)連続したアルカリ性エツチング液によりエツチン
グを行うので、製造効率を向上できる。
(4) Since etching is performed using a continuous alkaline etching solution, manufacturing efficiency can be improved.

(5)単結晶シリコン島の深さに合わせるマスクの角部
補償パターンの最適化が不要であり、設計を容易なもの
にできる。
(5) It is not necessary to optimize the corner compensation pattern of the mask to match the depth of the single crystal silicon island, and the design can be simplified.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)〜(e)は本発明の第1実施例を製造工程
順に示す断面図、第2図(a)〜(e)は本発明の第2
実施例を製造工程順に示す断面図、第3図は完成した半
導体装置の一例の断面図、第4図(a)、  (b)は
従来の異なる島構造を示す断面図、第5図(a)〜(e
)は従来の製造方法を工程順に示す断面図である。 1・・・単結晶シリコン基板、2・・・二酸化シリコン
膜、3・・・窒化シリコン膜、4・・・絶縁分離膜、5
・・・支持体層、6a・・・第1単結晶シリコン島、6
b・・・第2単結晶シリコン島、6C・・・第3単結晶
シリコン島、7a〜7c・・・マスク、8・・・開口、
9・・・台形溝、10・・・■溝、11〜13・・・素
子。 A−二
FIGS. 1(a) to (e) are cross-sectional views showing the first embodiment of the present invention in the order of manufacturing steps, and FIGS. 2(a) to (e) are cross-sectional views showing the second embodiment of the present invention.
3 is a sectional view of an example of a completed semiconductor device, FIGS. 4(a) and 4(b) are sectional views showing different conventional island structures, and FIG. )~(e
) is a sectional view showing the conventional manufacturing method in the order of steps. DESCRIPTION OF SYMBOLS 1... Single crystal silicon substrate, 2... Silicon dioxide film, 3... Silicon nitride film, 4... Insulating isolation film, 5
...Support layer, 6a...First single crystal silicon island, 6
b... Second single crystal silicon island, 6C... Third single crystal silicon island, 7a to 7c... Mask, 8... Opening,
9...Trapezoidal groove, 10...■groove, 11-13...Element. A-2

Claims (2)

【特許請求の範囲】[Claims] (1)単結晶半導体基板の表面に選択的に形成したマス
クを用いて前記半導体基板を部分的に異なる深さにエッ
チングし、その表面に絶縁分離膜及び支持体層を堆積し
た後前記半導体基板を裏面側から研磨して相互に絶縁分
離された異なる深さの単結晶半導体島を形成する絶縁分
離型半導体装置の製造方法において、前記単結晶半導体
基板のエッチングに際し、前記マスクは2種類以上の耐
エッチング被膜を各島領域に対応させて異なる組合わせ
の構造とし、これらマスクを用いて単結晶シリコン基板
を選択エッチングする工程と、これらマスクの耐エッチ
ング被膜を上層から順次除去する工程とを交互に行うこ
とを特徴とする絶縁分離型半導体装置の製造方法。
(1) After etching the semiconductor substrate to partially different depths using a mask selectively formed on the surface of the single crystal semiconductor substrate and depositing an insulating separation film and a support layer on the surface, the semiconductor substrate In the method for manufacturing an isolation type semiconductor device, in which monocrystalline semiconductor islands of different depths are formed and isolated from each other by polishing from the back side, when etching the monocrystalline semiconductor substrate, the mask is of two or more types. The etching-resistant coating is structured to have a different combination for each island region, and the process of selectively etching the single crystal silicon substrate using these masks and the process of sequentially removing the etching-resistant coating of these masks from the upper layer are alternately performed. 1. A method for manufacturing an insulation-separated semiconductor device, characterized in that the method comprises:
(2)エッチングにはアルカリ性水溶液を用い、耐エッ
チング被膜には二酸化シリコン膜及び窒化シリコン膜を
用いてなる特許請求の範囲第1項記載の絶縁分離型半導
体装置の製造方法。
(2) The method of manufacturing an isolation type semiconductor device according to claim 1, wherein an alkaline aqueous solution is used for etching, and a silicon dioxide film and a silicon nitride film are used as the etching-resistant film.
JP17883586A 1986-07-31 1986-07-31 Manufacture of dielectric isolation type semiconductor device Pending JPS6336545A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17883586A JPS6336545A (en) 1986-07-31 1986-07-31 Manufacture of dielectric isolation type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17883586A JPS6336545A (en) 1986-07-31 1986-07-31 Manufacture of dielectric isolation type semiconductor device

Publications (1)

Publication Number Publication Date
JPS6336545A true JPS6336545A (en) 1988-02-17

Family

ID=16055496

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17883586A Pending JPS6336545A (en) 1986-07-31 1986-07-31 Manufacture of dielectric isolation type semiconductor device

Country Status (1)

Country Link
JP (1) JPS6336545A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03245552A (en) * 1990-02-23 1991-11-01 Matsushita Electric Works Ltd Manufacture of insulating layer isolated board material
JPH05326682A (en) * 1992-05-15 1993-12-10 Matsushita Electric Works Ltd Manufacture of insulating layer isolation substrate
US6374362B1 (en) 1998-01-14 2002-04-16 Nec Corporation Device and method for shared process control

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03245552A (en) * 1990-02-23 1991-11-01 Matsushita Electric Works Ltd Manufacture of insulating layer isolated board material
JPH05326682A (en) * 1992-05-15 1993-12-10 Matsushita Electric Works Ltd Manufacture of insulating layer isolation substrate
US6374362B1 (en) 1998-01-14 2002-04-16 Nec Corporation Device and method for shared process control

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