JPH022962A - Method for facilitating test of very large scale integrated circuit - Google Patents

Abstract

PURPOSE:To impart a unified clock signal to all FFs without mixing a positive phase and an inverted phase and to make it possible to perform tests by inputting a test judging signal into a selector, selecting a specified test clock signal from the outside or an inner typical clock signal and an ordinary clock signal, and inputting the signal into the FF. CONSTITUTION:A test judging signal 11 which indicates whether normal operation is going on or testing operation is going on is inputted into a 2-1 selector 10 which is provided for every FF 20. A specified test clock signal 12 from the outside and an ordinary clock signal 13 are selected and inputted into the FF 20. The test judging signal 11 is inputted into the 2-1 selector 10. An inner typical clock signal 14 and the normal clock signal 13 are selected and inputted into the FF 20. In this way, the testing method of a very large scale integrated circuit in the following cases is made easy: in the case of the circuit constitution wherein many asynchronous inputs are present in the very large integrated circuit; in the case of the circuit constitution wherein many clock inputs are required; in the case of the circuit constitution wherein both phases of a positive phase and an inverted phase are used for one clock input signal and the like.

Description

[Detailed Description of the Invention] [1 Required] Regarding the testing method for very large-scale iK product circuits (VLSI), in the case of a circuit configuration in which there are many asynchronous inputs in the VLSI, there is a method for testing a circuit configuration that requires a large number of clock inputs. The purpose of this test is to simplify the VLSI verification method in the case of a circuit configuration that uses both positive and negative phases of one clock input signal. 2-1 provided for each flip-flop
The clock signal is input to a selector, and a specific external test clock signal, an internal representative test clock signal, and a normal clock signal are selected and input to the flip-flop.

[Industrial application field]

The present invention relates to facilitation of testing methods for very large scale integrated circuits (VLSI).

In very large scale integrated circuits (hereinafter referred to as VLSI), it is important to verify whether the manufactured circuit is normal. In this verification work, it is necessary to check whether all the logic elements in the VLSI are normal or not, and it is necessary to test by inputting various data to check whether or not they are made according to the logic, so the verification data is extremely large. It has become a huge amount.

[Conventional technology]

Conventional verification methods focus on flip-flops (FF) included in VLSI, and improve the flip-flops so that they can be configured as shift registers (SR) during verification work to reduce the amount of verification data. I try to do less.

The verification method in this case is to apply input for verifying the circuit to each input terminal, then set the VLSI to the verification state (that is, configure each flip-flop as a shift register),
The data of this flip-flop configured as a shift register is inputted to a special shift clocker used only when configuring a shift register to take it out of the VLSI, and at the same time, data for verification is input to this flip-flop configured as a shift register. Next, the VLSI is put into the normal operation verification state and normal operation is performed. This is a method of performing verification by repeating six or more operations in which the VLSI is put into the verification state again after a short period of normal operation and a special shift clock is input.

The above verification method is a method that has been used conventionally, but in this case, the normal clock inputs of all flip-flops are externally set to "L" level at the same time,
You have to reach the “■” level. The clock signal from the external clock terminal is V! , divide the frequency in Sl and use it as a clock for other flip-flops,
In cases where both the positive phase and negative phase of one clock signal are used as a clock, the above method cannot be used for verification. In addition, the upper limit of the number of external clock signals is set due to the limitations of actual VLSI testers, so it is difficult to detect asynchronous signals by using an asynchronous input signal as a flip-flop clock, or when the circuit scale is too large. In a very large VLSt, there may be cases where there is no unified clock in the VLSI, and a clock may exist for each functional block, and a very large number of clock signals may be required for one VLSI. be. These cases cannot be verified using conventional methods.

FIG. 3 shows an example of the configuration of VLS 1 in which these various logic circuits are combined. TRG■ and TRG■ indicate asynchronous input triggers, and CLK■ to ■ indicate various clock manual signals. Flip-flops 1 and 2 represent flip-flop circuits based on asynchronous manual trigger signals TRG■ and TRG■, flip-flops 3 and 4 represent flip-flop frequency divider circuits based on the CLK■ clock input signal, and flip-flop 5 represents a flip-flop circuit based on the CLK■ clock input signal. Flip-flop 6 is a flip-flop circuit for a clock input signal of CLK■, and flip-flop 7 is a flip-flop circuit for an OR circuit of clock signals CLK■ and CLK■. shows. Flip-flops 8 and 9 are parallel flip-flop circuits using a reverse phase input signal of the clock signal CLK■.
Therefore, when testing each flip-flop circuit, various trigger signals or clock signals must be supplied each time.

[Problem to be solved by the invention]

In the conventional VLSI verification method, when testing combinations of various logic circuits shown in Figure 3 above, one VLSI
requires multiple clock signals and trigger signals. Since these cases cannot be easily verified using conventional methods, the present invention uses a unified or lock signal at the time of testing.
The purpose is to verify that it is possible to apply normal phase and reverse phase to all flip-flops in an LSI without mixing them.

[Means to solve the problem]

FIGS. 1(a) and 1(b) show diagrams of the basic configuration of the present invention. Figure 1(a) shows the method of adding one external terminal to give a unified clock signal to all flip-flops, and Figure 1(b) shows the method of adding one internal clock signal to the remaining circuits. All of them are supplied as a clock, and each achieves this function by using a signal that indicates whether the VLSI is in normal operation or verification operation.

In the figure, 10 is a 2-2 circuit consisting of an AND circuit and an OR circuit.
1 selector, 20.30 is a flip-flop circuit, 40
indicates an inverter.

In the method of figure (a), the test judgment signal is set to 11, the external specific test clock signal is set to 12, and the normal clock signal is set to 13. In the method of figure (b), the test judgment signal (3
The number is 11, the internal representative clock signal is 14, and the other normal clock signals are 13.

[Effect]

In FIG. 1(a), the test judgment signal 11 is "11".
When the level is normal, the flip-flop 2
The 0 clock signal is selected by the AND circuit 15 on the upper side of the 2-1 selector 10, and the original normal clock signal 13 is transmitted as a clock signal to the flip-flop 20 via the OR circuit 17. When the level is “L”, the verification operation is in progress, and the flip-flop 20
The clock signal is selected by the inverter 40 to the AND circuit 16 on the lower side of the 2-1 selector 10, and the specific test clock signal 12 is transmitted via the OR circuit 17 as a clock signal to the flip-flop 20. therefore,
By specifying the test determination signal 11 as "11" or "L", each flip-flop can select a normal clock signal or a specific test clock signal.

In FIG. 1(b), the test determination signal 11 is “11#”.
When the level is normal, the flip-flop 2
The 0 clock signal is selected by the AND circuit 15 on the upper side of the 2-1 selector 10, and the original normal clock signal 13 is transmitted as a clock signal to the flip-flop 20 via the OR circuit 17. When the level is “L”, the verification operation is in progress, and the flip-flop 20
The clock signal 14 is selected by the inverter 40 to the lower AND circuit 16 of the 2-1 selector 10, and the representative clock signal 14 is passed through the OR circuit 17 to the flip-flop 20.
is transmitted as a test clock signal. therefore,
By specifying the test determination signal 11 as "11" or "L", each flip-flop can select a normal clock signal or a representative clock signal. Note that the flip-flop 30 can use the same clock signal 14 during normal operation and during verification operation.

〔Example〕

FIGS. 2(a) and 2(b) show circuit configuration diagrams of an embodiment of the present invention. Figure (a) shows a method of adding one external terminal to give a unified clock signal to all flip-flops, and Figure (b) uses one clock signal as a representative signal and applies this signal to the remaining other circuits. This is a method of supplying a signal as a clock, and both methods implement the functions of the present invention using a test determination signal indicating whether the VLS 1 is in normal operation or verification operation. Flip-flops 1 to 9 are conventional combinational logic circuits of flip-flops, which are implemented by adding a 2-1 selector 10 consisting of an AND circuit and an OR circuit to each flip-flop circuit.

In FIG. 2(a), a terminal for inputting a specific test clock signal TSCLK is provided in a conventional flip-flop combination circuit, and the test judgment signal TST is set to "11" or "L".
” and inputs it to the 2-1 selector lO provided for each flip-flop 1 to 9 to select a clock signal. In the case of test judgment signal T S T 11", each flip-flop 1 to 9 9 is a clock signal during normal operation, that is, TRG■, TRG■, CLK■~■
is selected and input to the CK terminal of each flip-flop.

When the test judgment signal TST is aLs, the inverter 40
, the lower AND circuit of the 2-1 selector 10 added to each flip-flop 1 to 9 is captured, a specific test clock signal TSCLK is input to the CK terminal of each flip-flop, and the 9 verification operations can be performed.

FIG. 2(b) shows a conventional flip-flop combination circuit using ■ as a representative test clock signal for CL-.
The test determination signal TST is inputted as "11" or "yes" and is inputted to the 2-1 selector lO provided for each flip-flop 4 to 9 to select a clock signal. When the test judgment signal TST is "11", each flip-flop 1 to 9 receives a clock signal during normal operation, TRG■
, TRG■, and CLK■-■ are selected and inputted to the CK terminal of each flip-flop to perform normal operation.

When the test judgment signal TST is “L”, the inverter 40
, the lower AND circuit of the 2-1 selector 10 added to each flip-flop 1 to 9 is captured, a representative test clock signal CLK■ is selected, and the signal is input to the CK terminal of each flip-flop. , each time a verification operation is performed. Note that flip-flop 3 also uses the normal clock signal CLK■ for testing, so CLK■
The signal is directly input to the CK Of child of the flip-flop.

In figure (b), the TRG ■ and ■ parts are shown in figure (a).
You may use a circuit similar to that of TRG■ and T
Except when checking the input buffer of RG■, T
Since equivalent results can be obtained by testing with the signal levels of RG■ and TRG■ fixed at the "high" level, this circuit is illustrated in FIG. 3(b).

In addition, by appropriately combining the methods shown in Figures (a) and (b),
The clock signals of all flip-flops in VLS1 are
It is also possible to perform unified control using about three clock signals.

〔Effect of the invention〕

Conventional methods can be used when there are many asynchronous inputs in VLSI, when many clock inputs are required, or when the circuit configuration uses both positive and negative phases of one clock input signal, etc. However, the method of the present invention has made it possible to verify all combinations of these circuit configurations.

[Brief explanation of the drawing]

FIG. 1 shows the principle configuration of the present invention, FIG. 2 shows the circuit configuration of an embodiment of the invention, and FIG. 3 shows the circuit configuration of a conventional example. In the figure, 1 to 9, 20.30 are flip-flops,
10 is a 2-1 selector, 11 is a test judgment signal, 12 is a test clock signal, 13 is a normal clock signal, 14 is a representative clock signal, 15.16 is an AND circuit, 17 is an OR circuit, and 40 is an inverter. (a) When an external clock signal is additionally used (b) When an internal clock signal is representatively used ) % Formula % Title of Invention Method for Facilitating Testing of Ultra-Large Scale Integrated Circuits 3゜Correction with Inno-1

Claims (1)

[Claims] 1. In the case of a circuit configuration in which there are many asynchronous inputs in a very large scale integrated circuit (VLSI), in the case of a circuit configuration that requires many clock inputs, the positive phase and opposite phase of one clock input signal In the case of a circuit configuration that uses both phases, a test judgment signal (11
), 2-1 provided for each flip-flop (20)
An ultra-large scale integrated circuit characterized in that an external specific test clock signal (12) and a normal clock signal (13) are input to a selector (10) and input to a flip-flop (20). Test facilitation method. 2. Test judgment signal indicating whether normal operation or verification operation is in progress (
11), 2 provided for each flip-flop (20)
-1 selector (10), an internal representative test clock signal (12) and a normal clock signal (13) are selected and input to the flip-flop (20). 1. The method for facilitating testing of a super large-scale integrated circuit according to 1.