JPH0740059B2 - Method for facilitating test of ultra-large scale integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Overview] Regarding a test method for a very large scale integrated circuit (VLSI), in the case of a circuit configuration in which a large number of asynchronous inputs are present in the VLSI, in the case of a circuit configuration requiring a large number of clock inputs, 1 For the purpose of facilitating the VLSI verification method in the case of a circuit configuration using both positive and negative phases of one clock input signal, a test judgment signal indicating whether the operation is normal operation or verification operation is performed. A specific external test clock signal or an internal representative test clock signal and a normal clock signal are selected as inputs to a 2-1 selector provided for each flip-flop and input to the flip-flop. .

[Industrial application field]

The present invention relates to facilitation of a test method for a very large scale integrated circuit (VLSI).

In a very large scale integrated circuit (hereinafter called VLSI), it is important to verify whether the manufactured product is normal or not. In this verification work, it is necessary to check whether all the logic elements in the VLSI are normal, and it is necessary to input various data to test whether the logic elements are in accordance with the logic. It has become a huge amount.

[Conventional technology]

As a conventional verification method, pay attention to the flip-flops (FFs) included in VLSI, and improve the flip-flops so that these flip-flops can be configured as shift registers (SR) during the verification work to reduce the verification data amount. I am trying to do it. In the verification method in this case, input for verifying the circuit is given to each input terminal, and then the VLSI is set to the verification state (that is, each flip-flop has a shift register configuration), and the data of this flip-flop configured , A special shift clock used only in the shift register configuration is input and taken out of the VLSI, and at the same time, verification data is input to the flip-flop configured in the shift register configuration. Next, the VLSI is set to the verification state in the normal operation and the normal operation is performed. After a little normal operation, VLSI is put into the verification state again and a special shift clock is input.
This is a method for performing verification by repeating the above operation.

The above verification method is a method that has been used conventionally, but in this case, the normal clock input of all flip-flops becomes "L" level from the outside at the same time,
You have to go to "H" level. When dividing the clock signal from the external clock terminal in VLSI and using it as the clock of other flip-flops, or when using both the positive and negative phases of one clock signal as the clock, It cannot be verified by the above method. In addition, since the upper limit of the number of clock signals given from the outside is set due to the limitation of the actual VLSI tester, when the asynchronous input signal is used as the clock of the flip-flop and the asynchronous signal is detected, the circuit scale is very large. In large VLSI, there is a case where there is no unified clock in VLSI and there is a clock for each functional block.
There are cases where a very large number of clock signals are required for one VLSI. These cases cannot be verified by conventional methods.

FIG. 3 shows an example of the structure of a VLSI in which these various logic circuits are combined. TRG and TRG indicate asynchronous input trigger,
CLK to indicate various clock input signals. Flip-flops 1 and 2 are asynchronous input trigger signals TRG and TRG
, A flip-flop circuit is shown by flip-flops 3 and 4, and a flip-flop 5 is shown by CLK.
Shows a reverse phase input flip-flop circuit of the clock input signal of, the flip-flop 6 shows a flip-flop circuit of the clock input signal of CLK, and the flip-flop 7
The flip-flop circuit by the OR circuit of CLK and the clock signal of CLK is shown. Flip-flops 8 and 9 are CLK
2 shows a parallel flip-flop circuit according to the reverse phase input signal of the clock signal of FIG. Therefore, when testing each flip-flop circuit, various trigger signals or clock signals must be supplied each time.

[Problems to be Solved by the Invention]

In the conventional VLSI verification method, a large number of clock signals and trigger signals are required for one VLSI when testing the combination of various logic circuits shown in FIG. In these cases, the conventional method cannot be easily verified. Therefore, in the present invention, a unified clock signal can be applied to all the flip-flops in the VLSI without mixing the positive and negative phases. The purpose is to verify.

[Means for Solving the Problems]

1 (a) and 1 (b) are diagrams showing the principle of the present invention. FIG. 1 (a) shows a method of adding one external terminal in order to give a uniform clock signal to all flip-flops, and FIG. 1 (b) shows one internal clock signal to the rest of the other circuits. This function is achieved by using a signal that indicates whether the VLSI is in normal operation or verification operation, by supplying all clocks.

In the figure, 10 is an AND circuit and an OR circuit 2-1.
Selectors, 20 and 30 are flip-flop circuits, and 40 is an inverter.

In the method of FIG. (A), the test determination signal is 11, the external specific test clock signal is 12, and the normal clock signal is 13, and in the method of FIG. The representative clock signal is 14, and the other normal clock signals are 13.

[Action]

In FIG. 1 (a), when the test determination signal 11 is at "H" level, the AND circuit 15 on the upper side of the 2-1 selector 10 is selected as the clock signal of the flip-flop 20 in the normal operation state. The normal clock signal 13 is transmitted as a clock signal of the flip-flop 20 via the OR circuit 17.
Next, when the test determination signal 11 is at the "L" level, the inverter 40 selects the AND circuit 16 below the 2-1 selector 10 as the clock signal of the flip-flop 20 while the verify operation is in progress. The clock signal 12 is transmitted as a clock signal of the flip-flop 20 via the OR circuit 17. Therefore, by designating the test determination signal 11 as "H" or "L", each flip-flop can select a normal clock signal or a specific test clock signal.

In FIG. 1 (b), when the test determination signal 11 is at "H" level, the AND circuit 15 on the upper side of the 2-1 selector 10 is selected as the clock signal of the flip-flop 20 in the normal operation state. The normal clock signal 13 is transmitted as a clock signal of the flip-flop 20 via the OR circuit 17.
Next, when the test determination signal 11 is at the "L" level, the inverter 40 selects the AND circuit 16 below the 2-1 selector 10 as the clock signal of the flip-flop 20 while the verify operation is in progress. The signal 14 is transmitted as a test clock signal for the flip-flop 20 via the OR circuit 17. Therefore, by designating the test determination signal 11 as "H" or "L", each flip-flop can select a normal clock signal or a representative clock signal. The flip-flop 30 can use the same clock signal 14 during the normal operation and the verification operation.

〔Example〕

2 (a) and 2 (b) are circuit configuration diagrams of an embodiment of the present invention. Figure (a) shows a method of adding one external terminal to give a uniform clock signal to all flip-flops, and figure (b) uses one clock signal as a representative signal and uses it for the rest of the other circuits. This is a method of supplying a signal as a clock, and is a method of carrying out the function of the present invention by using a test determination signal which indicates whether the VLSI is in normal operation or in verification operation. Flip-flops 1 to 9 are combinational logic circuits of conventional flip-flops, which are implemented by adding a 2-1 selector 10 composed of an AND circuit and an OR circuit to each conventional flip-flop circuit.

FIG. 2 (a) shows that a conventional flip-flop combination circuit is provided with a terminal for inputting a specific test clock signal TSCLK, and the test determination signal TST is input by "H" or "L", and the flip-flop 1 2 for each ~ 9
-1 Input to the selector 10 to select a clock signal. When the test judgment signal TST is "H", each flip-flop 1-9 is a clock signal for normal operation, that is, TRG.
, TRG, CLK ~ are selected and input to the CK terminals of the respective flip-flops.

When the test judgment signal TST is “L”, the two added to the respective flip-flops 1 to 9 through the inverter 40.
-1 Capture the AND circuit under the selector 10 and set the specific test clock signal TSCLK to the CK of each flip-flop.
By inputting to the terminal, the verification operation of the flip-flops 1 to 9 can be performed.

FIG. 2 (b) shows that a conventional flip-flop combination circuit uses CLK as a representative test clock signal and inputs a test determination signal TST by “H” or “L”, and the flip-flops 4 to 9 are respectively input. The clock signal is selected by inputting it to the provided 2-1 selector 10. Test judgment signal TST
Is "H", the flip-flops 1 to 9 select the clock signals, TRG, TRG, CLK, for normal operation, and input them to the CK terminals of the respective flip-flops to perform normal operation.

When the test judgment signal TST is “L”, the two added to the respective flip-flops 1 to 9 through the inverter 40.
It is possible to capture the AND circuit below the -1 selector 10, select the representative test clock CLK, and input it to the CK terminals of the respective flip-flops to perform the verification operation. Since the flip-flop 3 also uses the normal clock signal CLK for testing, the CLK signal is directly input to the CK terminal of the flip-flop.

Note that, in the figure (b), the same circuit as the circuit of the figure (a) may be used for the portion of TRG and TRG, except that TRG and the input buffer of TRG are checked.
An equivalent result can be obtained by testing the signal level of RG at a fixed "L" level, and therefore this circuit is shown in FIG.

In addition, by appropriately combining the methods of FIGS. (A) and (b),
It is also possible to integrally control the clock signals of all flip-flops in the VLSI by using a few clock signals.

〔The invention's effect〕

According to the configuration of the present invention, in the flip-flop circuit in the ultra-large scale integrated circuit, there is a clock signal for each functional block. It is possible to simplify the verification test method for ultra-large-scale integrated circuits by reducing the number of externally applied clock signals only during the verification test by using the signal indicating It will be possible.

[Brief description of drawings]

FIG. 1 is a principle block diagram of the present invention, FIG. 2 is a circuit block diagram of an embodiment of the present invention, and FIG. 3 is a circuit block diagram of a conventional example. In the figure, 1 to 9, 20, and 30 are flip-flops, and 10 is 2
-1 selector, 11 is a test judgment signal, 12 is a test clock signal, 13 is a normal clock signal, 14 is a representative clock signal, 15 and 16 are AND circuits, 17 is an OR circuit, and 40 is an inverter.

Claims (2)

[Claims] 1. A very large scale integrated circuit (VLSI) uses a plurality of asynchronous input flip-flop circuits, a flip-flop circuit requiring a plurality of clock inputs, and both positive and negative phases of one clock input signal. Test decision signal (11) indicating normal operation or verification operation when a flip-flop circuit and a parallel flip-flop circuit with negative phase input are included.
To a 2-1 selector (10) provided for each flip-flop (20) to select an external specific test clock signal (12) and a normal clock signal (13), 20) A method for facilitating the test of an ultra-large scale integrated circuit characterized by inputting into (20). 2. Use of a plurality of asynchronous input flip-flop circuits, a flip-flop circuit requiring a plurality of clock inputs, and both positive and negative phases of one clock input signal in a very large scale integrated circuit (VLSI). Test decision signal (11) indicating normal operation or verification operation when a flip-flop circuit and a parallel flip-flop circuit with negative phase input are included.
Is input to a 2-1 selector (10) provided for each flip-flop (20), and an internal representative clock signal (14)
Is used for testing, the representative clock signal (14) and the normal clock signal (13) are selected and input to a flip-flop (20), and a test facilitating method for an ultra-large scale integrated circuit is characterized. .