JPH02297221A - Executing speed control system for microprogram - Google Patents

Abstract

PURPOSE:To obtain a device having plural types of microprogram processing speeds with the use of only a single microprogram by selecting the optional microprogram executing speed based on the external switch setting information. CONSTITUTION:The initial value is set with the use of a switch 16 and then the execution of a microprogram process is started. Thus the initial value is set at a counter 17. The periodical interruptions are produced during the execution of a microprogram and a signal 108 becomes genuine. Then a microinstruction is executed and the output 109 of a microinstruction decoder 15 becomes genuine. Thus an FF 21 is set and the output 11 of an OR gate 20 becomes genuine. Consequently, the address updating operations of a microprogram sequencer 14 is temporarily stopped. Simultaneously, the selection mode of a selector 12 is changed to the selection mode of a NOP code 115 from the microinstruction selection mode of a microprogram store memory 11. Thus a NOP code is decoded by a decoder 15 and processed. This operation is stopped when the initial value is attained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a microprogram execution speed control system used in a microprogram control type information processing apparatus.

(Prior Art) Conventionally, in a microprogram control type information processing device, a circuit that controls the performance (execution speed) of the microprogram has been controlled by the microprogram (firmware) itself. In FIG. 3, 001 is a microprogram storage memory (CS), 002 is a microinstruction register (MIR) that holds microinstructions to be executed read from the microprogram storage memory 001, and 003 is
is a microprogram sequencer (
SQ) 004 is a microinstruction decoder (DEC) that decodes the microinstruction code 100 stored in the microinstruction register 002 and outputs control signals, etc. according to the code contents, and 005 is a microinstruction decoder (DEC) that decodes the microinstruction code 100 stored in the microinstruction register 002. Flip-flop set by interrupt signal 108 and reset by specific decode output 109 generated in the idle routine, 00B is flip-flop 0
When 05 is set, microinstruction decoder 0
This is an AND gate that outputs a "true" signal when there is a microinstruction decode output 105 indicating the end of a software instruction from 04, and uses this signal to move the generation address of the microprogram sequencer 003 to a specific address.

The execution speed control operation in the conventional microprogram control circuit shown in FIG. 1 will be explained with reference to the flow chart shown in FIG.

When a periodic external interrupt 108, such as from a timer, occurs while a series of microinstructions is being executed, the flip-flop 005 is set. Next, when the microinstruction decoder 004 generates a microinstruction decode output 105 indicating the end of the software instruction r, the output 103 of the AND gate 005 becomes "true", and the output 102 of the microprogram sequencer (103) is operated. As shown in FIG. 4, the address of the microprogram storage memory 001 is changed from address XXO2 to address ΔΔ01.

Then, in the idle routine shown in FIG. 4, a microinstruction that makes the decoded output 109 of the microinstruction decoder 004 "true" is executed, and the flip-flop 006 is reset. As a result, after executing a certain number of steps, the program returns to the address (XXO3 address) next to the original microprogram address (XXO2 address) and executes the next instruction.

As described above, the execution speed of the microprogram is controlled by periodically executing the idle routine.

In the conventional microprogram control mechanism described above, if you try to realize an information processing device with multiple types of microprogram processing speeds with a single hardware configuration, it is necessary to This required a microprogram with idle routines each having a different number of steps, which caused the problem that the microprogram became complex.

(Problems to be Solved by the Invention) As mentioned above, conventionally, when realizing an information processing device with multiple microprogram processing speeds using the same hardware configuration, it is necessary to There is a problem in that an idle routine with a large number of steps is required, which makes the microprogram complicated.

The present invention has been made in view of the above circumstances, and provides an information processing device adopting a microprogram control method.
It is an object of the present invention to provide a microprogram execution speed control method that can realize a device having multiple types of microprogram processing speeds using a single hardware configuration and one type of microprogram.

[Structure of the Invention] (Means and Effects for Solving the Problems) The present invention provides an information processing device that employs a microprogram control method, in which an arbitrary microprogram execution speed can be adjusted according to external switch setting information. It has a configuration that allows you to choose.
It has a counter whose initial value can be set using an external switch.
The operation of the microprogram sequencer is temporarily stopped in response to periodic interrupts from the outside and the status of the microinstructions, and a no-operation code is inserted into the execution microinstructions using hardware to continue execution. By returning control of the execution of microinstructions to the microprogram sequencer at the timing when the value of the counter reaches a constant value, a means for controlling the microprogram execution processing speed is realized.

By realizing such a microprogram execution speed control method, when realizing a device with multiple types of microprogram execution speeds with a single hardware configuration, it is possible to implement the same number of steps as the types of speeds. There is no need for microprograms having different numbers of idle routines, and an apparatus having multiple types of microprogram processing speeds can be realized using only one type of microprogram.

(Example) An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In FIG. 1, 11 is a microprogram storage memory (CS), which reads a microinstruction (microcode) 101 to be executed in accordance with a microinstruction read address 100 generated from the microprogram sequencer 14.

12 receives the microinstruction 101 read from the microprogram storage memory 11 and the NOP code 115, which is a type of microinstruction given from external hardware, and selectively selects one of them according to the output 111 of the OR gate 20. This is a selector that outputs to .

13 is a microinstruction register (MIR) that holds microinstructions to be executed, output from the selector 12;
It is.

14 is a microprogram sequencer (SQ) that generates the read address 100 of the microprogram storage memory 11, and when the signal input to the enable terminal (EN) indicates the enable state (that is, the output lit of the OR gate 20 is When it is “false” (-0”)
updates the address in synchronization with the basic clock (B-CLK), but when the signal input to the enable terminal (EN) indicates a disabled state (that is, the output 111 of the OR gate 20 is "true"). (-“1”), the same address continues to be output.

15 is a microinstruction decoder (DE) that decodes the microinstruction (microcode) stored in the microinstruction register 13 and outputs a control signal etc. according to the contents of the code.
C).

16 is an operation switch (S
W), which is set and operated before the microprogram is executed.

17 is a counter (CTR) that executes the count operation of the set idle routine with the set value of switch 1B as the initial value.
), and the signal input to the load terminal (L) is “true”
When the set count value 105 of the switch 1B is set and the signal input to the count enable terminal (CE) indicates the enable state (that is, the set side output terminal (Q) signal of the flip-flop 21 is When the count operation of the set idle routine is completed, the count output terminal (C
A) outputs a count end signal 10B.

18 is an interrupt signal 1 that occurs periodically such as a timer interrupt.
07 is received at the set input terminal (S), and the count end signal 106 output from the counter 17 is received at the reset input terminal (R
), the count end signal 1 is generated from the generation of the interrupt signal 107 to the end of the count operation of the set idle routine.
Until the generation of 0B, the signal 10 at the set side output terminal (Q)
This is a flip-flop that takes 8 as “true”.

Reference numeral 19 indicates that when the flip-flop I8 outputs a signal 108 indicating execution of an idle routine, the microinstruction decoder 15 outputs a decode signal 109 of a microinstruction (see FIG. 3(c)) indicating the end of a software instruction. This is an AND gate that outputs a “true” signal.

20 receives the output signal 110 of the AND gate 19 and the signal of the set side output terminal (Q) of the flip-flop 2I, and when either signal is "true", selects the NOP code 115 by the selector 12. This is an OR gate that switches to the mode and controls to stop updating the address of the microprogram sequencer 14.

21 receives the output of the AND gate 19 at the set input terminal (S), and receives the count end signal 1 output from the counter 17.
This flip-flop receives 0B at its reset input terminal (R) and outputs a "true" signal from its set side output terminal (Q) during the idle routine.

The signal at the set side output terminal (Q) of this flip-flop 21 is connected to the count enable terminal (CE) of the counter 17.
and is supplied to the OR gate 20.

22 receives the count end signal 10B outputted from the count output terminal (CA) of the counter 17 and the signal 113 which becomes "true" at the beginning of the microprogram running.
It is an OR gate that supplies each of these signals to the load terminal (L) of the counter 17 as a load enable signal.

2 and 3 are for explaining the operation of the above embodiment, respectively. FIG. 2 is a flowchart illustrating the microprogram steps, and FIG. 3 is a flowchart illustrating the microprogram steps shown in FIG. 3 is a time chart showing the state of each part when a typical interrupt 107 occurs.

In FIG. 2, Sl is a step for executing address C of the microprogram, and one software instruction ends here. When the microinstruction is executed at this time, when the microinstruction decoder 15 outputs the decode signal 109 indicating the end of the software instruction r, the NOP code 11
5 starts the final execution speed control process. or,
In FIG. 3, a, b, c, . . . g are microinstruction read addresses (+00) output from the microprogram sequencer 14, and (a), (b),
(c).

...(g) is the above microinstruction read address ab
, c, ...g, microprogram storage memory 1
．． This is a microinstruction (101) read from 1.

Further, in FIG. 3, B-CLK is a basic clock, and microprogram processing operations are executed in synchronization with this basic clock.

The operation of the above embodiment will now be described with reference to FIGS. 1 to 3.

First, when executing the microprogram processing, the length (initial value) of the idle routine is set by operating the switch 1G.

Then, when you start executing the microprogram processing,
The initial value set by operating the switch 16 is set in the counter 17 by the signal 113 which becomes "true" at the start of the microprogram.

During the execution of a series of microprograms, when a periodic interrupt by a timer or the like occurs and the signal 107 becomes "true", the flip-flop 18 is set, and the signal at the set side output terminal (Q) of the flip-flop 18 is set. 108 becomes "true" (see FIG. 3).

Thereafter, when the microinstruction (C) shown in FIG. 3, which indicates the end of one software instruction, is executed and the output 109 of the microinstruction decoder 15 becomes "true", the output 110 of the AND gate 19 becomes "true". Accordingly, the flip-flop 21 is set and the output Ut of the OR gate 20 becomes "true" (see FIG. 3).

The output signal (111-'true#) of the OR gate 20 causes the address update operation of the microprogram sequencer 14 to be temporarily stopped, and the selection mode of the selector 12 is changed from the microinstruction selection mode of the microprogram storage memory 11 to the NOP code. The selection mode is switched to 115, and furthermore, the counter 17 is placed in a count enable state.

As a result, while the flip-flop 21 is in the set state, the NOP code 115 given by hardware is selected by the selector 12 and the microinstruction register 13
After being stored in , it is decoded by the microinstruction decoder 15 and processing according to the NOP code 115 is executed.

The counter 17 continues its counting operation, and when it completes the counting operation of the set idle routine according to the initial value loaded from the switch 16, it outputs a count end signal (106-true") from the count output terminal (CA).

As a result, the set value of the switch 1G is loaded into the counter 17 again as an initial value, and the flip-flops 18 and 21 are both reset, and the output of the OR gate 20 changes from "true 0" to "false".This signal change ( 11■
- "true" - "for"), the address update operation of the microprogram sequencer 14 that had been stopped at - is restarted, and the selection mode of the selector 12 is changed to NOP.
The selection mode of the code 115 is switched to the microinstruction selection mode of the microprogram storage memory 11,
The next microinstruction (d) following the above microinstruction (C) is read from the microprogram storage memory 11,
Execution of the microinstruction processing stored in the microprogram storage memory 11 is resumed.

In this way, according to the value set by the external switch 16,
NOP code given externally by hardware +1
By realizing a microprogram execution speed control method that executes the processing in step 5, it is possible to realize a device with multiple types of microprogram execution speeds using a single hardware configuration. There is no need for microprograms having the same number of idle routines with different numbers of steps, and an apparatus having multiple types of microprogram processing speeds can be realized using only one type of microprogram.

[Effects of the Invention] As detailed above, according to the microprogram execution speed control method of the present invention, the microinstruction code read from the microprogram storage memory and the N given from the outside are
a selector for receiving an OP code and selecting one of them; means for setting an execution period of an idle routine using a NOP code; periodic interrupts given from the outside; and software instructions read from a microprogram storage memory. In response to the execution output of the code indicating the end of the code, updating of the address of the microprogram storage memory is stopped, and the selector is changed from the selection mode of the code read from the microprogram storage memory to the selection mode of the NOP code given from the outside. a logic circuit that switches to
means for detecting that the instruction execution period according to the NOP code selected by the selector has reached the execution period of the set idle routine;
A logic circuit that switches from the code selection mode to the microinstruction food selection mode read from the microprogram storage memory and resumes address updating of the microprogram storage memory is installed, and according to external switch setting information, any microinstruction code is selected. By adopting a configuration in which the program execution speed can be selected, when realizing a device with multiple types of microprogram execution speeds with a single hardware configuration, it is possible to create an idle device with the same number of steps as the type of speed. A device having multiple types of microprogram processing speeds can be realized using only one type of microprogram without requiring a microprogram with a routine.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIGS. 2 and 3 are for explaining the operation of the above embodiment, respectively, and FIG. 2 is a flowchart illustrating microprogram steps, and FIG. FIG. 3 is a time chart showing the state of each part when a periodic interrupt occurs when the microprogram shown in FIG. 2 is executed. FIG. 4 is a block diagram showing the configuration of a conventional microprogram control circuit.
FIG. 5 is a flowchart showing a conventional microprogram execution speed control processing flow. 11...Microprogram storage memory (CS), 1
2... Selector, 13... Micro instruction register (
MIR), +4...Micro program sequencer (
S Q), 15-Ficro Instruction Decoder (DEC),
1B-Switch (SW), 17-Kan') 9 (CT
R), 18, 21... flip-flop, 19...
And gate, 20, 22...or gate, 115.
...NOP code. Applicant's Representative Patent Attorney Takehiko Suzue

Claims (1)

[Claims] a selector for receiving a microinstruction code read from a microprogram storage memory and a NOP code applied from the outside and selecting one of them; means for setting an execution period of an idle routine using the NOP code; In response to the given periodic interrupt and the execution output of a code indicating the end of the software instruction read from the microprogram storage memory, updating of the address of the microprogram storage memory is stopped, and the selector is read from the microprogram storage memory. A logic circuit switches from a selected code selection mode to an externally given NOP code selection mode, and detects that the instruction execution period according to the NOP code selected by the selector has reached the idle routine execution period set above. means for detecting, and when the means detects the end of execution of the idle routine, switches the selector from a NOP code selection mode to a microinstruction code selection mode read from the microprogram storage memory; A microprogram execution speed control method comprising: a logic circuit for restarting address updating.