JPH02298023A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enhance a punchthrough voltage and to prevent an increase in a junction capacitance by a method wherein a first impurity and a second impurity are implanted nearly perpendicularly into a face of a semiconductor substrate and a third impurity is implanted obliquely into the face of the semiconductor substrate. CONSTITUTION:A poly-Si gate electrode 18 and a sidewall SiO2 film 17 are formed on a P-type Si substrate 15; after that, arsenic ions and phosphorus ions are implanted from a direction nearly perpendicular to a face of the Si substrate 15 by making use of the poly-Si gate electrode 18 and the sidewall SiO2 film 17 as a mask; boron ions are implanted obliquely into the face of the Si substrate 15. After that, a heat treatment is executed; the implanted ions are diffused; an N<+> type region 19 and an N-type region 20 are obtained; a P-type region 21 is formed at a curved part of the N-type region 20. During this process, the N<+> type region 19 is made nearly as deep as the P-type region 21, and the N-type region 20 is made deeper than the N<+> type region 19.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a method of manufacturing a semiconductor device, and more specifically, to a method of forming a source and drain of a field effect transistor.

(b) Conventional technology FIG. 5 shows a triple diffused drain n-channel MO according to a conventional example.
FIG. 3 is a cross-sectional view illustrating a method of manufacturing an S transistor.

As shown in Figure A, a poly-Si gate electrode (4) formed on a P-type Si substrate (1) and a sidewall Si
As4 (arsenic ion) using O, film (3) as a mask.

P" (phosphorous ions) and B" (boron ions) are implanted almost perpendicularly to the surface of the Si substrate (1>).

Next, as shown in Figure B, each ion is activated by heat treatment and diffused to a predetermined depth. (5) is an N+ type region with a high concentration mainly made of arsenic ions, and is used to obtain ohmic contact with source/drain electrodes (not shown). 7) is an N-type region with a high concentration of phosphorus ions, which has been formed deeper than the N"-type region (5) to prevent hot electrons. (6) is a P-type region made of boron ions. This is to increase the bunch-through voltage between the source and drain.

(c) Problems to be Solved by the Invention By the way, since the P-type region (6) is provided to improve the bunch-through voltage between the source and the drain, it should be controls the spread of That is, the depth of downward diffusion is not much considered.

Therefore, a new PN junction is formed between the P-type region (6) and the N-type region (7), which have a higher impurity concentration than the Si substrate (1), and the transistor operation speed slows down due to increased junction capacitance. There is a problem.

The present invention was made in view of such conventional problems,
The present invention aims to provide a method for manufacturing a semiconductor device that can improve bunch-through voltage and prevent increase in junction capacitance.

(d) Means for Solving the Problems As shown in the diagram explaining the principle of the present invention in FIG. a first impurity (e.g. arsenic ion) and a second impurity (e.g. phosphorus ion) substantially perpendicularly to the
and a third impurity (for example, boron ions) is implanted obliquely to the surface of the semiconductor substrate (8>), and as a result of the diffusion process, the depth of the first impurity is Xl, and the depth of the third impurity is Impurity depth Xl.

The depth X12 of the second impurity is made deeper than the depth Xi of the first impurity.

As a result of obliquely implanting the third impurity (11), the diffusion elongation of the third impurity (11) is greatest in the oblique direction, resulting in a diffusion profile shown by the broken line in the figure.

<*) Effect FIG. 2 is a diagram for explaining the present invention in detail. That is,
According to the present invention, as a result of obliquely implanting the third impurity (for example, boron), in this direction the first N-type impurity region (
12) and diffuses into the second N-type impurity region (13). In this way, the third P-type impurity region (14
) can be formed only at the corners of the curved portion of the first N-type impurity region (12). Therefore, expansion of the depletion layer when a source-drain voltage is applied can be suppressed, and bunch-through voltage can be improved. At the same time, since no P-type impurity region is formed at the lower end of the first N-type impurity region (12), no new PN junction is formed. Therefore, the problem of increased capacity seen in the conventional example can be solved.

(F) Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

FIGS. 3A to 3C are explanatory diagrams of a method for manufacturing a semiconductor device according to an embodiment of the present invention. First, as shown in figure A, P type S
A poly-Si gate electrode (
18) and sidewall 5i0. After forming the film (17), using the poly-Si gate electrode (18) and the sidewall Sin film as a mask, arsenic ions,
Phosphorus ions are implanted from a direction substantially perpendicular to the surface of the Si substrate (15) (FIG. 1B). The injection conditions at this time are
For example, for arsenic ions, the implantation energy is 60Ke.
V, dose amount 5 X 10 "Cm-"1? , 60 eV for phosphorus ion, I x 1014 crr
The implantation direction is slightly tilted (7°±3°) to prevent ion implantation channeling.

Also, the boron ion is 80KeV, 3 X 10”c
m-'', and the injection direction was tilted at 30°.

FIG. 4 is a cross-sectional view for generally explaining how to decide the implantation direction of boron ions, and (19) shows a high concentration N1 type region mainly formed by arsenic ions,
(20) is a low concentration N-type region formed by phosphorus ions. In addition, xIl is the downward diffusion distance of the N2 type region, point A is the point where the lower diffusion end of the N'' type region (19) is extended horizontally and intersects with the diffusion end of the N type region (19), and point B is the side This is the point where the line Q passing through the edge of the wall and perpendicular to the surface of the 5i substrate (8) intersects with the surface of the Si substrate (8).Rp is the distance between points A and B, and d is the point. This is the distance between A and the line Q. Note that xIl is the distance of downward diffusion of the N-type region (20), and l is the angle (incident angle) between the boron ion implantation direction and the Q line.

The direction of implantation of boron ions can be determined as follows.

Since the impurity profile of the N-type regions (19) and (20) is determined by the impurity ion implantation conditions and diffusion conditions, Xll+d is obtained. This allows tan
The direction of boron injection is determined from i''d/XHt.

Also, the diffusion distance Rp of boron after heat treatment is R, mx Shoulder! Since it can be determined by + d 1, boron ion implantation conditions (dose amount, energy) can be determined based on this.

After that, heat treatment is performed in N gas at 950°C for 50 minutes to diffuse the implanted ions, resulting in N
“Type region (19) (X, I-0, 2 μm).

An N-type region (20) (x, *-0,25 μm) is obtained. A P-type region (21) is then formed at the curved portion of the N-type region (20).

Thus, according to the embodiment of the present invention, the N-type region (20)
P-type region (21) only in the curved part of (source/drain)
is formed, it is possible to increase the bunch-through voltage between the source and drain while suppressing an increase in the PN junction capacitance between the source and drain, thereby increasing the operating speed of the transistor.

As described in detail, according to the present invention, boron ions can be implanted obliquely so that they can be formed only at the corners of the curved portion of the N-type region (19).

Therefore, the extension of the depletion layer generated when a voltage is applied between the source and drain can be suppressed, and the bunch-through voltage between the source and drain can be improved.

Furthermore, since no P-type region is formed outside the lower end of the N-type region (20), an increase in PN junction capacitance can also be prevented. Therefore, the operating speed of the transistor can be increased compared to the conventional transistor.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view explaining the present invention in detail, FIG. 2 is a cross-sectional view explaining the present invention in detail, FIGS. 3A to C are cross-sectional views explaining the present invention in detail, and FIG. A cross-sectional view explaining the direction of ion implantation, and FIGS. 5A and 5B are cross-sectional views explaining a conventional example.

Claims (2)

[Claims] (1) In a method for manufacturing a semiconductor device in which impurities are implanted using the gate electrode portion as a mask to form a source/drain in a self-aligned manner, a semiconductor device of an opposite conductivity type is implanted from a direction substantially perpendicular to the surface of a semiconductor substrate of one conductivity type. A third impurity of one conductivity type is implanted obliquely to the semiconductor substrate surface, and after heat treatment, the first impurity is diffused downward. the depth and the depth of downward diffusion of the third impurity are approximately equal;
A method for manufacturing a semiconductor device, characterized in that the depth of downward diffusion of the second impurity is made deeper than that. (2) The method of manufacturing a semiconductor device according to claim 1, wherein arsenic and phosphorus are used as the first and second impurities, and boron is used as the third impurity.