JPH02299008A - Timer circuit - Google Patents

Abstract

PURPOSE:To prevent a software or hardware mode load from being applied by outputting a signal which inhibits timer data from being read out during carry operation. CONSTITUTION:This real-time clock inputs the clock T1Hz obtained by dividing the frequency of a reference clock CLK32kHz as the clock of an FF3 and a busy signal BTCBUSY goes up to an H level at the rise of this clock T1Hz to inhibit the timer data from being read out. At a point T2 of time after this point T1 of time, the output of the FF2, i.e. a timer clock RTC1Hz goes up to the H level, so that a timer counter 4 enters carry operation. Further, reset outputs of respective stages of a frequency divider 1 go up to the H level respectively 1/16ms after the point T2 of time and an FF3 is cleared. The timer data is therefore allowed to be read out. Thus, this simple constitution inhibits the timer data from being read out during the carry operation.

Description

DETAILED DESCRIPTION OF THE INVENTION Object of the Invention (Field of Industrial Application) The present invention relates to a timer circuit that is applied to, for example, a real-time clock and performs a timekeeping operation.

In conventional real-time clocks, timer data such as February 1st, day of the week, 2 hours, 9 minutes, 1 second, etc., generated by a timer circuit is read out sequentially, and the timer data is not carried up while reading the timer data. If this is done, there is a risk that the read timer data will be incorrect.

Therefore, in order to prevent such incorrect timer data being obtained, conventionally, the read timer data is compared with the previously read timer data, and if they are different, the timer data is read again from the beginning. We are doing so-called double reading.

This double reading is performed, for example, by the process shown in FIG. That is, when the control unit enters the timer data reading process, first, in step 4a, the digit to be read (hereinafter referred to as the read digit) is determined to be the "1 second" digit, and then in step 4b, the timer data of the read digit is determined. Read data (n). Then, in step 4c, the timer data n read out in step 4d is compared with the timer data (m) read out last time.

Here, if timer data n and timer data m match, it is determined in step 4d whether reading of all timer data has been completed.

Here, if reading of all timer data has been completed, the process returns to the main routine. If reading of all timer data has not been completed, the process moves to step 4e, and in step 4e, the read digit is changed to the next digit (for example, "1 second" digit = "10 second" digit = "1 hour digit"). ” digit = “10
"time" digit (set in the order of "1 year" digit → "10 year" digit), and repeat the process from step 4b onward.

On the other hand, if timer data n and timer data m do not match in step 4C, there has been a carry of the read digit, so the process moves to step 4f, and in this step 4f, timer data n is changed to timer data m. and then return to the main routine.

In this way, when a carry is performed during timer data reading and the timer data reading process is completed, the control section enters the timer data reading process again from the main routine and performs the above-mentioned process.

Therefore, in some cases, the process shown in FIG. 4 must be repeated many times, resulting in a very large processing overhead.

Another method for preventing incorrect timer data is to disable the operation of the timer circuit to prevent carry from occurring while reading timer data, or to provide a clock synchronization circuit. There is a method of detecting the rising edge of a timer clock (I Hz) and issuing an interrupt to the control unit.

However, the former method requires a clock hold circuit and may cause a delay in timing by the timer circuit. Furthermore, if the power is turned off while the timer circuit is in the disabled state, it will malfunction, so it is necessary to add means for detecting power-down and enabling the timer circuit.

Furthermore, in the latter of the two methods described above, a clock synchronization circuit, an interrupt controller, and the like must be provided, which imposes a burden on the hardware.

(Problem to be Solved by the Invention) As described above, in the conventional timer circuit, it is possible to prevent the read timer data from becoming incorrect due to a carry of the timer data while the timer data is continuously being output. Because of this, there have been problems such as increased processing overhead, increased hardware load, and delays in time measurement.

The present invention has been made in consideration of these circumstances, and its purpose is to be able to prohibit the reading of timer data during carry while having a simple configuration, and to provide a software and hardware-friendly To provide a timer circuit which is not subject to any physical load and which does not cause a delay in time measurement.

[Structure of the Invention] (Means for Solving the Problems) In the present invention, a signal (busy signal) for inhibiting timer data reading is output at least during carry.

(Function) By taking such measures, a signal that prohibits data reading is output at least during carry, so the side that reads timer data from this timer circuit outputs the signal that prohibits data reading. By monitoring the timer data and reading the timer data during a period when the signal prohibiting data reading is not output, the timer data will not be read out during carry.

(Embodiment) Hereinafter, a timer circuit according to an embodiment of the present invention will be explained with reference to the drawings.

FIG. 1 is a diagram showing the configuration of a real-time clock constructed by applying the same timer circuit. In the figure, 1 indicates 15 D-flip-flop circuits (hereinafter referred to as FF) la
It is a frequency divider with a well-known configuration composed of 10 to 10, and the reference clock CLK3 is input to the first stage FF1a.
2 KHz (frequency 32.788 KHz) is divided by 15 to generate an IHz clock T I Hz. The clock TIHz generated by this frequency divider 1 is input to the input terminal of FF2 and the clock terminal of FF3, and
Now, set output of FF1b T8KHz (frequency 8.1
9KHz) by synchronizing with the rising edge of
Shifted by 16+as, timer clock RTCIHz
It is said that This timer clock RTCIHz is input to a timer counter 4 having a well-known configuration, and is used for timekeeping operation.

FF3 generates a busy signal RTCBUSY as a signal for inhibiting reading of timer data, and outputs a signal at rHJ level during the period from the rising edge of the clock TIHz until it is cleared. In response to the busy signal RTCBUSY output from the FF 3, the busy flag in the status register 5 is set to 0N10FF.

6 is a NAND gate, and FF1 of the first stage of frequency divider 1
a reset output T16KHz (frequency 16.384K
Hz) and reset output T8K of second stage FF1b
Hz, and the set output T4KHz (frequency 4.098 KHz) of the third stage FF1c are input, respectively.

The output of this NAND gate 6 is input to the clear terminal of the FF 3 via an AND gate 7. In addition, AND
A reset signal RESET is also input to the gate 7. Here, the AND gate 7 is of negative logic, takes the logical sum of the output of the NAND gate 6 and the reset signal RESET, and outputs the result as a clear signal for the FF3.

Next, the operation of the real-time clock configured as described above will be explained with reference to the time chart shown in FIG.

In this real-time clock, the reference clock CL K
IHz clock TI obtained by dividing 32 KHz by 15
Hz as the clock of FF3, and this clock T
The busy signal RTCBUSY becomes rH at the rising edge of IHz.
It becomes J level and reading of timer data is prohibited.

(as of T1).

When 1/16 is passes from this time T1 and reaches time 12, the output of FF2, that is, the timer clock RT C
111z becomes the rHJ level, so the timer counter 4 performs a carry.

Furthermore, when 1/16+as has passed from this 12 time point (time point T3), the reset output T 16 KIIz of the first stage FF1a of the frequency divider 1 and the second stage F F i b
The reset output T8 KHz of the third stage F F 1 c and the set output T 4 KHz of the third stage F F 1 c are respectively at the rHJ level, and the output of the NAND gate 6 is at the rLJ level. As a result, the output of the AND gate 7 also becomes "L" level, and the FF3 is cleared. Therefore, the busy signal RTCBUSY output from FF3 becomes "L" level, and reading of timer data is permitted.

In this way, the rise time T2 of the timer clock RTCIHz, that is, 1/1 before and after the carry time, respectively.
Busy signal RTCBUSY is rHJ for 6+ms
level, and reading of timer data is prohibited.

Therefore, the present real-time clock control section (not shown) performs timer data read processing, for example, as follows. That is, as shown in FIG. 3, the busy flag of the status register 5 is checked in step 3a, and it is determined whether the busy flag of the status register 5 is "1" in step 3b.

Here, if the busy flag is "1", step 3a
Repeat the check of the check flag and wait until the busy flag becomes "0".

When the busy flag becomes "0" in step 3b, all timer data is read out at once in step 3C without checking whether there is a carry or not, and this is set as the current timer data.

As described above, according to this embodiment, the busy signal RTCBU is output for 1/16 IIls before and after the carry time.
Since SY becomes rHJ level and the busy flag of status register 5 is set to "1", the control section of this real-time clock can read the correct timer data by the very simple processing described above, and the software and no additional hardware is required. Further, since there is no need to stop the timekeeping operation, there is no possibility that there will be a delay in timing.

Note that the present invention is not limited to the above embodiments.

For example, in the above embodiment, the busy signal RTCBUSY is
The period when the HJ level is set is a period of 1/16 is (1/8 ms) before and after the rising time of the timer clock RTCIHz, but this period can be any length of time as long as it includes the rising time of the timer clock RTCIHz. It's okay. Further, in the above embodiments, the timer circuit according to the present invention is applied to a real-time clock, but it is also possible to apply it to other devices such as a timer counter circuit or a programmable interval timer. In addition, various modifications can be made without departing from the gist of the present invention.

[Effects of the Invention] According to the present invention, a signal for prohibiting reading of timer data at least during carry is output, so that it is possible to prohibit reading of timer data during carry despite the simple configuration. The present invention provides a timer circuit that does not impose any burden on software or hardware, and that does not cause time delays.

[Brief explanation of the drawing]

1 to 3 are diagrams for explaining a timer circuit according to an embodiment of the present invention, and FIG. 1 is a diagram showing the configuration of a real-time clock configured by applying the timer circuit, and
3 is an operation time chart, FIG. 3 is a flowchart showing an example of timer data read processing, and FIG. 4 is a diagram explaining a conventional technique. 1... Frequency divider, 1a to 1o... D-flip-flop circuit (FF), 2.3... D-flip-flop circuit (FF), 4... timer counter, 5... status Register, 6...NAND gate, 7...
AND gate.

Claims (1)

[Claims] A timer circuit comprising means for outputting a signal for inhibiting reading of timer data at least during carry.