JPH02299053A - Priority control system for plural fifo information storage devices - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] For example, regarding a read priority management method for a plurality of FIFO storage devices for temporarily holding input information in a unit in a common bus system, it is possible to prevent processing suppression due to ID overflow. In order to reduce the number of times and improve the throughput of the entire system, in response to the input information signal and the write target instruction signal, at least two
An IFO type storage device, a counter that issues an ID and supplies it to the ID storage section of the FIFO type storage device, an ID overflow detection device provided corresponding to the FIFO type storage device, and when the counter does not overflow, When there is a priority determination device that determines storage information according to a predetermined priority order, an output selection device that selects one storage information based on the output of the priority determination device, and input instructions to the same FIFO type storage device are received in succession. , is configured to include a write target storage device that prevents the counter from being updated.

[Industrial Field of Application] The present invention is applicable, for example, to a common lotus system in which a unit includes a plurality of FIFO storage devices for temporarily holding human information, and the read priority order among the storage devices and the The present invention relates to a priority management method when the processing order must be determined taking into account the order in which input information is received.

FIG. 2 shows a block diagram of a system to which the present invention is applied. In the figure, CPs indicated by blocks 11 and 12
U(1) and CPU(2) are central processing units, CH(1) denoted by blocks 13, 14, 15, respectively.
, CH(2), and CH(3) are channels, respectively.

In addition, MAC16 is a memory access controller, M
SU 17 is the main storage, these are MSU 1
All but 7 are connected to the common bus on 1st. In this system, both the CPU system processing device and the CH system processing device are MAC1.
MSU 17 is accessed via 6. In this case, the present invention is used in cases where priorities are added to processing requests from the CPU-based processing device and processing requests from the CH-based processing device.

[Prior Art] As described above, when the MSU 17 is accessed from the CPU and CH, a FIFO type storage device (abbreviated as a stack) is used as a buffer. FIFO means first in, first out. The most basic type having only one input stack can simply process the input order, and there is no problem. In the conventional technology when a plurality of input stacks are provided, each time input information is stored, 10 (unique number) for order management is updated and issued, and this is stored together with the input information. Then, at the time of taking it out from the stack, the respective management IDs are compared to determine the priority order.

FIG. 4 shows a block diagram of a device that performs a conventional priority management system using a plurality of stacks.

The stack consists of an input information storage device and an ID storage device,
Reference numbers 11.1-2.1-3 and 24.2 respectively
-2.2-3 are numbered. In addition, this device includes a sequence management ID generation device 3, an ID overflow detection device (OF) 4-1.4-2.4-3, a priority determination device (determination) 5, and an output selection device (selection). 6.

In the above device, each time there is a write request, [D
The generator 3 receives the write target signal and updates the ID to generate the signal, and the input information is stored in one of the input information storage devices of a plurality of stacks, and the corresponding ID is stored in the ID storage device of that stack.

The ID information taken out from the ID storage device is always compared with the latest ID output by the ID generation device 3 by the ID overflow detection device. All of the ID information taken out from the ID storage device and the comparison information output from the ID AutoN flow detection device are sent to the priority determination bag W5. The determination device 5 determines the priority order based on this information and sends a selection signal to the output selection device 6, or outputs an ID overflow signal when the ID overflows/<flows and stores it in the stack. suppress. ID overflow occurs when the ID generator 3 reaches the maximum value and is then cleared since it has a finite number of digits.

[Problem to be solved by the invention] In the conventional device described above, it is difficult to manage the I/O for each write.
If D is updated, since the size of the management ID is finite, there is a possibility that processing of a specific stack will progress and ID duplication will occur. In order to avoid this, a means is required to detect ID overflow and suppress writing. Suppressing writes reduces overall system throughput. However, if an attempt is made to avoid this by creating a single stack, a problem arises in that it is not possible to set priorities among input information.

An object of the present invention is to update the ID only when the stack to be written changes, thereby reducing the number of times processing is suppressed due to an overflow of 10, and improving the throughput of the entire system.

Furthermore, by selecting an ID generator with an appropriate number of digits especially when the number of stacks is two, it is possible to omit an ID overflow detection device, thereby realizing hardware simplification.

[Means to solve the problem]

In the present invention, as illustrated in FIG. 1, a priority management system for a plurality of FIFO information storage devices is provided. In this method, upon receiving the input information signal and the write target instruction signal, the information storage units Ll and 1 are respectively stored.
-2.1-3 and ID storage units 2-1 and 2 representing ranks
-2.2-3; a counter 3 that receives at least two FIFO type memory word memory write target instruction signals having a number of 2-3, issues the ID, and supplies the ID to the FIFO type memory word memory storage unit; an ID overflow detection device 4-1゜4-2.4-3 which is provided as a FIFO type memory word storage device and detects an overflow of the counter;
When the counter 3 does not overflow in response to the output of the IFO type memory word storage unit and the output of the ID overflow detection device, a plurality of F
a priority determining device 5 for determining stored information of the IFO type mnemonic word storage device; and an output selecting device 6 for receiving the output of the priority determining device 5, selecting the one stored information and outputting it as an output information signal. , and a write target storage device 7 which receives the write target instruction signal and controls the counter 3 not to be updated when an input instruction is received in the same FIFO type memory word storage device.

Further, in one embodiment of the present invention, a priority management system for a plurality of FIFO information storage devices as illustrated in FIG. 3 is provided. In this method, in response to an input information signal and a write target instruction signal, information storage sections 1-1, 1-2 and 10 storage sections 2 representing the rankings are used.
- receiving two FIFO type memory word memory write target instruction signals having numbers 1 and 2-2, and issuing the ID;
a counter 3 for supplying to the FIFO type memory word storage storage unit; and two FIFO type memory word storage units that receive the output of the FIFO type memory word storage unit and the output of the counter 3 according to a predetermined priority order. a priority order determining device 5 that determines the stored information of the priority order determining device 5; an output selecting device 6 that receives the output of the priority order determining device 5, selects the one stored information and outputs it as an output information signal; and the writing target instruction signal. The write target storage device 7 is configured to control the counter 3 not to be updated when an input instruction is received in the same FIFO type memory word storage device.

[For production]

According to the present invention, when there are three or more stacks, the order management ID is not updated every time, so that suppression of ° processing due to ID overflow is less likely to occur.

If there are two stacks, the number of IDs required can be determined according to the depth of the stack, so if the required size OID size page area is six, overflow will be eliminated.

Therefore, an ID overflow detection device is not required.

[Embodiment] FIG. 1 shows a block diagram of a device that performs a priority management system in a plurality of FIFO information storage devices as a first embodiment of the present invention.

This device is input information storage device 1-L 1-2.1-3
．． ..., ID storage device 2-1.2-2.2-3.・・・
・Sequence management ID generation device 3, ID overflow detection device (Ko) 4-1, 4-2゜4-3. ..., a priority determination device (determination) 5, an output selection device (selection) 6, and a write target storage device 7. A FIFO type storage device (stack) is configured by a plurality of pairs of input information storage devices and ID storage devices.

Since the details of this device other than the write target storage device 7 have been described in detail in the related art, they will be omitted here.

The device 7 receives the write target designation signal, holds it, compares the write target designation signal with the stored previous write target, and if they do not match, sends an ID update request signal to the ID generation device 3. 9 is sent, and when it loses, the output of the ID generator 3 is not changed. In this way, when successive writes are made to one stack, the ID
Suppress number increase, reduce overflow frequency,
Moreover, within the same stack, it is first-in, first-out, so the same ID
But there is no risk of getting the ranking wrong.

An apparatus for carrying out a second embodiment of the invention is shown in FIG. This device has two stacks, and unlike the first embodiment, the ID overflow detection device is omitted. There is also a register (RUG 1-1.REG) at the output of the stack.
1-2) have been inserted, but this is not important to the invention. In the apparatus shown in FIG.
connected to.

The order management ID generation device 3 represented by a broken line block is a cyclic counter that generates an updated ID by incrementing it one by one. The register portion of the counter is designated C. The circled +1 represents the incrementer portion of the counter. This incrementer receives the signal from device 7 (
It operates only when ID update request signal) 9 is on. The counter should be long enough so that even if the two stacks are filled, there will be no duplicate IDs. For example, if stacks (1) and (2) both have a capacity of 4 stages, the most ID will be consumed when both stacks are used alternately, and the contents of the ID storage device in that case are, for example, It will look like Table 1. Therefore, the counter (C) should have a width of 3 bits as shown in Table 1 Stack (1) Stack (2) Counter.

The priority determination device 5 in the block surrounded by a broken line includes a circuit for detecting circulation indicated by "comparison" in the figure, and a circuit for "judgment" in the figure.
It consists of the actual priority determination circuit shown in . For example, assuming that the priority of stack (1) is higher than stack (2) and the processing of stack (1) can overtake the processing of first-arrived stack (2), but the reverse is not possible, the next state in the state shown in Table 1 It is conceivable that conditions such as those shown in Table 2 will appear.

In such a case, simply comparing the stack (1) with 0
Stack (1) Stack (2) Table 2 Stack (1) Stack (2) Since the counter appears to be earlier than 1 in stack (2), it is necessary to take into account the comparison result with the counter when making a decision. Specifically, if it is determined that the comparator outputs 1 when the read ID is larger than the counter value, a logical relationship as shown in Table 3 is obtained.

Table 3 The write target storage device 7 surrounded by a broken line is +STK S
In order to hold the stack selection signal (target instruction signal) indicated by EL, 0FF (furi, 7buflo, ump) and FF
It consists of a logic circuit for checking the mismatch between the output signal of and the signal +STK SEL. If the two signals do not match, the output signal of the OR circuit shown in the figure is turned on. Also STK
The signal indicated by IN is a write request signal for the stack, and the AND of this signal and the output signal of the previous OR circuit is outputted to the outside of the block as an ID update request signal. The signal (-CI, K) is a clock signal.

According to the above configuration, as long as writing continues to the same stack, the same 10 is issued, and when writing to a later stack, an updated ID is issued. Furthermore, even if IDs are circulated, the order relationship can be correctly reproduced and no duplication occurs.

〔Effect of the invention〕

According to the present invention, by updating the ID only when the stack to be written changes, it is possible to reduce the number of times processing is suppressed due to ID overflow and improve the throughput of the entire system.

Furthermore, when the number of stacks is 2, by selecting a [D generating device with an appropriate number of digits, it is possible to omit the ID overflow detection device and realize hardware simplification.

[Brief explanation of the drawing]

FIG. 1 shows a plurality of FIFOs as a first embodiment of the present invention.
FIG. 2 is a block diagram of a system in which the present invention is used; FIG. 3 is a block circuit diagram of a device implementing the second embodiment; FIG. is a block circuit diagram of a conventional device. In the figure, 1-1.1 to 2.1-3... input information storage device, 2-
1.2-2.2-3...iD storage device, 3...order management ID generation device, 4-1, 4-2.4-3...10 overflow detection device, 5...priority These are a ranking determination device, 6... an output selection device, and 7... a writing target storage device.

Claims (1)

[Claims] 1. In response to the input information signal and the write target instruction signal, information storage units (1-1, 1-2, 1-3) and ID storage units (2-1, 2 -2, 2-3), receiving the write target instruction signal and issuing the ID;
a counter (3) supplied to the ID storage section of the FIFO type storage device; an ID overflow detection device (4-1, 4-2, 4) provided corresponding to each of the FIFO type storage devices to detect an overflow of the counter; -3) When the counter (3) does not overflow in response to the output of the ID storage section of the FIFO type storage device and the output of the overflow detection device, one of the plurality of FIFO type storage devices is selected according to a predetermined priority order. Priority determination device (5) that determines storage information
, upon receiving the output of the priority determining device (5),
an output selection device (6) that selects one piece of stored information and outputs it as an output information signal; and a counter (3) when there is a continuous input instruction to the same FIFO type storage device in response to the write target instruction signal. Write target storage device (7) that is controlled not to update
A priority management method in a plurality of FIFO information storage devices comprising: 2. Two FIFOs each having an information storage section (1-1, 1-2) and an ID storage section (2-1, 2-2) representing the rank, each receiving an input information signal and a write target instruction signal.
a type storage device, receiving the write target instruction signal and issuing the ID;
a counter (3) that supplies the ID storage section of the FIFO storage device; and a counter (3) that receives the output of the ID storage section of the FIFO storage device and the output of the counter (3), and supplies the two FIFO storage devices according to a predetermined priority order. a priority determination device (5) that determines one piece of stored information of the device; an output selection device (6) that receives an output from the priority determination device (5), selects the one piece of stored information, and outputs it as an output information signal. ), and a write target storage device (7) that receives the write target instruction signal and controls the counter (3) so as not to update when there are successive input instructions to the same FIFO type storage device.
A priority management method in a plurality of FIFO information storage devices comprising: