JPH02299489A - Servo circuit - Google Patents

Abstract

PURPOSE:To achieve a sufficient resolution by dividing the feedback period of motor speed and phase error signal into sufficiently large blocks thereby carrying out PWM in a unit of time which causes no practical trouble. CONSTITUTION:Content of a counter 78 is inputted in parallel into a register 161 and a counter 162 with rising timing of FF10 pulse being fed from a terminal 150. The counter 162 produces an MSB signal having same frequency as T5 thus setting a flipflop 166 through a differentiation circuit 165. PWM modulation for single 0 clock is carried out at the locations allotted through AND gates 167-170. Additional bit data collected through an OR gate 180 set the flipflop 166 through an OR gate 178 and PWM wave allotted with additional bits is produced at an output terminal 182. By such arrangement, PWM is carried out in a unit of time which causes no practical trouble and a sufficient resolution can be achieved.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a method for pulse width modulating (hereinafter abbreviated as PWM) the output of a digital error detector (counter) of a servo circuit, particularly a digital servo circuit.

Digital information detected as an error in a drum servo system such as a VTR must ultimately be fed back as a drive signal for a servo motor and converted into an analog quantity. For this reason, PWM is optimal as a D-A conversion method for converting the output information of the digital error detector into an analog quantity.

In this case, considering the drum drive motor of a VTR, the motor speed detection signal is, for example, a PG signal that occurs six times per rotation, so 30X6=180
The output information of the error detector is created by comparing the signal detected every Hz with the reference signal and modulating it, which is
It is converted to a WM signal. In this case, the problem is PW
When PWM is performed by changing the ratio of "1" to "0" every 1807 times, which is the period of the M signal, when the PWM signal is applied to the motor via a low-pass filter, this low-frequency This is very undesirable since the servo system will have a large phase delay due to the phase caused by the filter.

Therefore, even if the motor speed is detected every 180 Hz, the faster the PWM cycle in the DA conversion, the better for the servo system.

However, since PWM modulates the signal with the ratio of "1" to "0", the problem is the minimum unit time that determines this ratio, which causes a quantization error in the D-A converter. .

For example, if a dynamic range of 60 db is required for the motor voltage, the minimum unit time is s 6 x 1024 (60 db
) 456 MHz, which is PWM
This is not desirable because the speed of the counter that generates the signal is extremely fast.

On the other hand, the resolution of 60db is 60db for 1807.
Since it can be considered as the resolution of db, the PW of 56KHz
32db for M period (unit time 3.58MH
It can be seen that for the remaining 18 db as z), any request can be covered by further time-sharing the PWM cycle.

In view of such circumstances, the present invention aims to provide a PWM' method that can obtain sufficient resolution while performing PWM in a unit time that does not cause any practical problems. When using PWM, the PWM period itself is sufficiently fast, while the dynamic range that appears as a quantization error is sufficiently wide to satisfy the requirements of the servo drive circuit, and the quantization (unit time) during the PWM period is practically In order to be able to select a problem-free value, the feedback period of the motor speed and phase error signal is divided into sufficiently large blocks, and each block is modulated by one bit of PWM. It is characterized in that it modulates the PWM signals as uniformly as possible, or focuses on a specific block and modulates several bits of it all at once.

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, a servo circuit to which the present invention is applied will be described below with reference to the drawings.

In general, the most commonly used circuit system for equipment that requires servo control for a drive motor (for example, a VTR) generates a ramp voltage from a reference signal (or controlled signal), and generates a ramp voltage from the controlled signal. (or reference signal), sample and hold the ramp voltage, and use it as the terminal voltage of the motor to be controlled.

FIG. 1 is a block circuit diagram of such a conventional servo system, and 10 is a terminal for receiving a tacho pulse representing the rotation of the motor 12. This tacho pulse, that is, the controlled signal PG (controlled object) shown in FIG. A signal generated from 12, V
In the case of TR, this is achieved by a magnet attached to a rotating head drum and a fixed coil.
Of course, the signal from the frequency generator FG may also be used. ) is waveform shaped by the waveform shaping circuit 14, and then the first monomulti 1
6, given to the second monomulti 18.

These Mono Multi 16.18 and Mono Multi 2 described later
8 is provided for the purpose of correcting residual errors of the servo that cannot be fully controlled, so as not to restrict the mounting position of the PG coil or magnet, and to prevent the mounting accuracy from becoming strict. Figure 2 shows the output waveform of the first monomulti 16.
2g shows the output waveform after passing through the second monomulti 18 and the lamp voltage generation circuit 20. 26 in FIG. This is necessary to achieve a constant rotational phase relationship, and may normally consist of a crystal oscillator, line power frequency source, etc.
Shows the synchronous waveform. 28 is the above-mentioned monomulti, 3o is a sampling pulse generation circuit, and each output waveform is the second one.
Shown in Figures g and f. The sampling pulse from the sampling pulse generation circuit 30 is outputted to the second circuit section 32.
As shown in Figures g and f, the ramp portion of the ramp voltage generation circuit 20 is sampled. FIG. 2g shows the motor voltage when the sampled voltage is applied to the motor 12 via the hold circuit 22 and the motor drive amplifier 24. The differential voltage level ΔE between the applied voltages E and E2 indicates the servo error voltage.

In contrast to the servo method, which generates an error by sampling the lamp voltage, there is a digital error detector. Several methods can be considered for configuring this digital error detector, and some are already known. The principle of this digital error detector will be explained below with reference to the timing chart of FIG.
Since the purpose of the servo is to keep the time interval (period of It I It in Figure 3 g) between the double signal (g) in Figure 3 and the reference signal V synchronization signal (period of It I It in Figure 3 g) to a certain value, the digital type counts this time interval T using a sufficiently fast clock, and determines whether it is smaller or larger than the target number based on the count result. In FIG. 3, a counter clock is generated during a time interval T as shown in FIG. 3d, and a counter consisting of N bits counts the number of clocks. In Figure 3, e is the counter 1-bit output CT, f is the counter 2-bit output CT2, and g is the counter N-bit output C.
Indicates TN. In Fig. 3C, the most significant bit CTN of the counter at the end of #1 tj and the synchronization edge.
should be in any one of ■, ■, and ■ as shown in Figure 3g, where ■ indicates that the T spacing is too wide, ■ indicates the optimal spacing, and ■ indicates that the T spacing is too narrow. This is the result of selecting the clock frequency or the number of counter stages so that when the target time interval T reaches, the counters complete one cycle and all become "'O". Therefore, in the analog system related to FIGS. 1 and 2, the servo error is obtained directly as a voltage value, but in the digital system, the servo error is given as a digital value as a count value. Therefore, the servo error given as a digital value needs to be converted into an analog voltage in some way before being given to the motor.

Methods for converting into such an analog voltage include a method using a DA converter and a method using PWM (pulse width modulation). In the latter method, when sampling the center of the lamp voltage using the analog method described above, that is, when the phase relationship between PG and V synchronization is optimal,
0'' ratio, or duty, is 50:50, or 1, and it is designed to have the same value as the analog system after passing through a filter and converting to DC voltage.Then, due to the error obtained in the digital value, This PWM “1”, It O”
By varying the ratio, it is possible to perform functions completely equivalent to analog systems. At this time, the PWM repetition period must be selected to such a value that the phase delay caused by the filter for converting to DC voltage can be ignored with respect to the frequency at which the error occurs.

Since a servo circuit consisting of such a PWM type digital error detector can basically be realized entirely using logic circuits, 1) highly accurate control can be achieved;

2) Adjustments due to variations in parts can be avoided.

3) No change in temperature or over time.

4) High integration is possible.

However, on the other hand, a quantization error due to the clock frequency always occurs, and as a result, it becomes an error element for the servo, so the design must be such that it does not affect the servo.

Next, before describing the rotary head drum servo circuit of a VTR, which is the object of the present invention, the original role of the drum servo will be explained. When constructing a drum servo for a VTR using a DC motor, the focus is on a phase servo that sets the position of the video head of the drum in a constant phase relationship with a specific reference signal.

Furthermore, as a matter of course, in order for one phase to match, the speeds must match, and at the same time, a speed servo is also required.

In other words, in a VTR, the velocity servo loop can be considered to play a necessary role in applying phase servo. It also has the role of damping, which controls the speed so that it does not deviate greatly from the speed change from the phase servo loop when locking one phase, and speeds up the pull-in. This speed loop is not necessary when using an AC motor that can basically be expected to have constant speed. FIG. 4 shows a timing chart of this phase servo. FIG. 4a shows the PG indicating the position of the video head, and FIG. The one-phase servo, which may be a reference signal such as a 30-7 crystal frequency source, maintains the phase φ of the reference signal on the PG signal at a constant phase. Of course, the reference signal at this time differs depending on the recording/playback mode of the VTR, and also depending on whether tracking is performed using a drum or capstan. However, the principle of keeping the phase φ constant in FIG. 4 remains the same.

Figures 5 and 6 show a VTR constructed according to the principles described above.
These are circuit diagrams of the drum servo, in particular, FIG. 5 shows the speed servo part, and FIG. 6 shows the phase servo part. terminals 50 and 52
The PGA and PGB signals provided to the rotary head drum are two rotational speed tacho pulse information from big-off coils approximately 18 degrees apart that cooperate with, for example, six pole pieces mounted equidistantly around the rotating head drum. Therefore, P.G.
The A and PGB signals each occur as six tacho pulses per rotation of the rotating head drum. The PGA is configured to precede the PGB.

The amplified PGA signal is amplified by each of the PG doubler signal amplifiers 51 and 53, and the amplified PGA signal is sent to the speed servo delay circuit 54.
The PGB signal, which is delayed by a predetermined amount and applied to the set input of the flip-flop 56 and amplified, is applied directly to the reset input of the flip-flop 56. This delay circuit 54 is for simplifying the counting operation and configuration when counting the time length between the PGA and PGB signals with a counter and making the counted value correspond to the speed command voltage applied to the motor. It's not necessarily necessary.

On the other hand, cascaded flip-flops 58 and 60 are provided. A set input of flip-flop 58 receives the amplified PGB signal, and a set input of flip-flop 60 receives the output of flip-flop 58. Output FF11 of flip-flop 60. becomes the reset input for these two flip-flops 58.60. A timing signal Ti, which will be described later, is applied to the clock input CP of the flip-flop 60 on the output line 6 of the clock generation counter 62.
Given from 2a.

This counter 62a has a 3.58 MHz crystal 64, for example, and generates timing clock signals of four different frequencies. Line 62b generates a clock *0 of 3.58 MHz, line 62c generates a clock *1 of frequency *O/4 (895 KHz), and line 6
2d is a clock with a frequency of *O/32 (& to 112) *
Generates 2.

The clock *0 on the output line 62b is provided as a clock input CP of a counter 66 having, for example, 1024 bits. The MSD signal indicating the maximum bit position of the counter or the timing at which the counter returns to O is applied as a falling bit to the differentiating circuit 68 as shown, and then becomes a reset pulse for the flip-flop 70. On the other hand, the timing pulse Ti on the output line 62a becomes a set input to the flip-flop 70. flip flop 7
The output FF2 of 0 is a PWM output, the period of which is determined by the Ti clock, and the reset pulse MSD determines the duty ratio, that is, the energizing power level to the motor 76.

The on/off output of the flip-flop 70 is converted into a direct current by an integrator 72, and then power amplified by a motor drive amplifier 74.

The buffer counter 66 is reset in a manner described below,
This reset timing changes the timing of the reset signal of the PWM flip-flop 70, and therefore changes the motor energizing power level.

The timing of resetting the buffer counter 66 is determined by the MSD output of the speed detection counter 78. This counter 78 is also 1 like the buffer counter 66 mentioned above.
This counter 78, which may be a counter with 0.24-bit configuration, is configured to output FF1 by AND gate 82 and FF1 by AND gate 84.
The *0 clock strobed by the ゜ output and the ×1 clock strobed by the MDF output from the phase servo part, which will be described later, are ORed by the AND gate 86 and the OR gate 88
It is received at the clock input CP via the clock input CP.

In addition, the amplified PGA signal is used as the reset signal.
It is received as a PGA'' signal from the GA amplifier.

The MSD falling output of the counter 78 is differentiated by a differentiating circuit 90, then synchronized with the FFL output by an AND gate 80, and then provided to the buffer 7 counter 66 as a reset input.

Figure 6 shows the phase servo circuit part, whose output is MDF
The signal is applied to the speed circuit section of FIG. 5 as the MDF input of AND gate 86. A terminal 100 is supplied with a tacho pulse PGC representing the rotational phase of the rotary head drum from a pickoff device associated with a pole piece fixed to the one-rotation head drum, and a -right terminal 102 is supplied with a reference pulse serving as a phase reference. The PGC signal at terminal 100 is connected to the set input of flip-flop 108 via amplifier 104 and delay circuit 106, while the PGC signal at terminal 102
A phase reference pulse of is applied to the reset input. That is,
The output of flip-flop 108 is indicative of the phase difference (including a fixed delay) of the rotary head drum relative to the reference phase; this flip-flop output provides a strobe signal of *2 clocks at AND gate 110.

On the other hand, FF1 of the speed control loop. Two cascaded flip-flops 112, 114 are provided which provide synchronization signals FF, □ as well as outputs. The circuit configuration is the same as that of the velocity loop flip-flop 58.60 described above, except that the set input of the first flip-flop 112 receives the phase reference pulse.

The FF and 1 outputs of the flip-flop 114 act as x0 clock strobe signals in the AND gate 116, and the outputs of the AND gates 110 and 116 act as the OR gate 1.
18 as a clock input to a phase error detection counter 120.

This counter 120 is, for example, a 256-decimal counter,
The amplified PGC signal, that is, the output PGC' of the amplifier 104
reset by . The MSD output in the form of a falling edge of the counter 120 is passed through a differentiator circuit 122 to the AN
synchronized with the FFo output at D gate 124;
It is then applied to the reset input of the phase loop buffer counter 126.

The counter 126 is, for example, a 256-decimal counter,
A shift signal T SFT, which will be described later, is applied to the D gate 128.
*1 clock strobed with AND gate 130
FF,, the XO clock strobed with the signal O
It is received as a clock input via R gate 132. The MSD falling edge of counter 126 is differentiated by differentiator circuit 134, and this output pulse is applied to the reset input of flip-flop 136. The set input of flip-flop 136 receives the PGA' signal and its output provides the MDF signal that is applied to the velocity loop.

The above-mentioned T'spτ signal is sent to the flip-flop 140, A
This is obtained by a circuit consisting of an ND gate 144, for example a 256-base counter 142. flip flop 140
A PGA' signal is applied to its set input, and a signal indicating that the count value of the counter 142 has reached the 256-decimal count value is applied to its reset input. flip flop 1
The Q output of 40 outputs the T SFT signal, and the output provides a signal to reset counter 142. counter 14
2 receives at its clock input the *1 clock strobed with the T SFT signal.

FIG. 7 is a waveform diagram for explaining the operation of the digital servo consisting of the velocity and phase loops shown in FIGS. 5 and 6, in which (a) is the PGC signal applied to the terminal 100,
) is the PGA signal given to terminal 50, (C) is the PGA signal given to terminal 5
(d) is the phase reference signal (for example, a V synchronization signal whose frequency is divided by 1/2) that is applied to the terminal 102.One PGC signal is generated per drum rotation, so there is a difference between the PGC pulses. refers to the time it takes for one rotation of the drum.

Further, there are six PGA and PGB pulses each during one drum rotation period, that is, between PGC pulses.

(a) shows the operating waveform of the phase loop, and (e-1) is the output of the delay circuit 106, which rises at the position of the PGC pulse and falls after a predetermined amount of delay.

(e-2) shows the output waveform of the flip-flop 108, that is, it rises at the fall of the delay circuit output in (e-1) and falls at the V synchronization signal position in (d). (a-3)
shows the waveform of the output of the flip-flop 112, which rises at the V synchronization signal position and falls at the arrival of the timing signal Ti.

(e-4) shows the waveform of the output FF, 1 of the flip-flop 114, which is set at the reset time of the flip-flop 112 and reset when the next Ti timing pulse arrives. Therefore, the phase error associated with the phase difference between P G Ct<rus at terminal 100 and the phase reference pulse at terminal 102, or the pulse period (e
-2) is initially counter 1 associated with *2 clock
20, and then during the count of ×0 clocks in the middle of the period of F F, 1, the counter 120
produces an output. In other words, the larger the amount of one phase error, the longer the output period of the flip-flop 108 becomes.

×゛Since the count amount is 22, FF, 1 period (Ti
The x1 count amount in the cycle (period) becomes smaller, and therefore the timing of the MSD output of the counter 120 becomes earlier. AN
The D gate 124 works to ensure that the MSD differential pulse always occurs within the period F F, . Therefore, the phase loop buffer counter 126 has a reset timing that is changed depending on the magnitude of the phase error. The phase error detection counter 120 is reset at the timing of each PGC signal, ie once for each rotation of the head.

Therefore, the phase loop buffer counter 126 must introduce phase error information, or the MFD signal, into the velocity loop six times for each rotation of the head.

For this purpose, the T SFT signal is used for controlling the clock input of buffer counter 126. In Figure 7 (
f-4) shows the waveform of this T SFT signal.

This T SFT pulse is caused by the arrival of each PGA pulse, and during the T SFT pulse the buffer counter 126
is required to rotate once. That is, the buffer counter 126 is configured to hold the measured phase error six times. The MSD output of buffer counter 126 is provided to the reset input of flip-flop 136 in six continuations of error information associated with the output of phase error detection counter 120.

Therefore, the MFD output of flip-flop 136 will turn on with the arrival of the PGA signal and will have a period representing the phase error.

(f-1) in FIG. 7 shows the output of the PGA signal delay circuit 54 of the speed loop in FIG. 5, (f-2) shows the output FF1 of the flip-flop 56, and (f-3) shows the MD
FIG. 8 is a waveform diagram in which the time position of the signal g in FIG. 7 is enlarged to include other signals.

Figure 8 (a) shows the PGA signal, (b) shows the PGB signal, (c
) is the output of the delay circuit 54 which rises in response to the PGA signal and falls after a predetermined specific time; (d) is the output of the flip-flop 56 which is set in response to this falling and reset in response to the PGB signal. It is FF□. (
e) is the MDF signal from the phase loop and has a rising period representing a phase error due to the PGA signal. P.G.A.
The speed detection counter 78, which is reset by the ' signal, counts *1 clock during this MDF signal period. That is, a phase term is introduced into the velocity loop by changing the initial value of the count value of counter 78. (f) is T
The SFT signal is similarly used for the purpose of rising in response to the PGA signal for a predetermined length, that is, for the phase loop buffer counter 126 to rotate six times as described above.

The speed detection counter 78 also detects X during the period of the signal FF1.
Count one clock. As mentioned above, the period of FF□ represents the speed term. Therefore, the speed detection counter 7
8 means that the number of clocks corresponding to the phase and velocity terms was counted at the fall position of the FF signal.

FIG. 8(g) shows the Ti signal that determines the PWM period,
(h) shows an FF which is the output of the flip-flop 70 for generating PWM output. FF rises at the position of the Ti timing pulse and falls at the end of a period depending on the phase and magnitude of the velocity term.

(i) is the output FF of the flip-flop 58.

This rises with the arrival of the PGB pulse and then falls with the occurrence of the Ti timing pulse.
j) rises in response to the fall of FF and the next Ti
FF, which falls according to the timing pulse. This FF shows the signal. The signal is provided to AND gate 84;
The *0 clock is supplied to the clock input of the speed detection counter 78 via the OR gate 88 by strobing the clock *O. FF. In the middle of the period, the counter 78 is full-up due to the supply of the *0 clock, and thereby the counter 78 outputs an MSD falling edge, which resets the speed loop buffer counter 66. This causes the MSD edge of this buffer counter 66, thereby determining the timing of the fall position (position indicated by the arrow) of the FF signal.

The subsequent fall position of the FF follows the fall of the buffer counter until the arrival of the next reset pulse.

From the above explanation, I think you have understood that the results of the digital error detector shown in FIGS. 5 and 6 are output in the form of a PWM wave (FFL).

In this example, 3.58MHz is used as *0, and PWM
The frequency of the wave is approximately 3.5 at the frequency of the timing signal Ti.
KHz (dynamic level 60db).

The present invention is applied when it is desired to make this cycle faster.

In the present invention, the output of the counter 78 is not only the MSD output but also the contents of the previous bit.

That is, FIG. 9 shows an embodiment of the present invention, in which the circuit after the counter 78 in FIG. 5 has been improved so that the output corresponding to the FF becomes P.
It is obtained as WM2.

That is, at the timing of the rise of the FF1° pulse input from the terminal 150, the contents of the counter 78 are input in parallel to the 4-bit register 161 and the 64-base counter 162. The register 161 contains the lower 4 of the counter 78.
The bits are input through AND gates 151 to 154, respectively, and the upper six bits are input to AND gates 155 to 154.
60 to the counter 162.

Furthermore, a 64-decimal counter 163 and a 4-bit counter 164
is provided, and the counter 63 produces a pulse train T5 having a frequency 16 times that of the preceding Ti. Also counter 1
62 also counts clocks *O, so it outputs an MSB signal with the same frequency as T, and sets a flip-flop 166 via a differentiating circuit 165.

Naori counters 163 and 164 are pulse FFs.

It is reset at the rise of . The contents of counter 164 are named Na-N, and the contents of register 161 are named B0-B, and AND gates 167-
Logic is taken at 170. This gate will perform the allocation of additional bits. PWM modulation for one ×O clock is performed at this allocated location. Therefore, a D-type flip-flop 171 is provided. The timing signal T is the differentiating circuit 173 and the inverter 17.
5 to an AND gate 177, and the output of the flip-flop 171 is applied to a differentiating circuit 172 and an inverter 17.
4 to AND gate 176. Also OR
The additional bits of data collected by gate 180 are applied directly to AND gate 176 and via an inverter to AND gate 177. Therefore, when an additional bit is attached, an output is obtained from the AND gate 176, and when it is not attached, an output is obtained from the AND gate 177, and the flip-flop 166 is reset via the OR gate 178, so that the PWM wave to which the additional bit is finally assigned is It is obtained from the output terminal 182. Note that 179 is a differential circuit.

FIG. 10 is a time chart for understanding the present invention. 10A shows the timing signal Ti, B shows the timing signal T, and C1 to C4 show the outputs N0 to N of the counter 164.
, and D is FF engineering. The signals E-E in FIG. 10 represent the contents B, -B of the register 161, and the positions of the additional bits are determined according to the logic of AND gates 167-170. F1-F indicate the timing of additional bits added according to codes B3-B6, and the total is indicated by F5. Before the FF1° pulse started, it was 83~B, but it was (1011) and the FF was working. After B stands,
~B, is changed to (0101).

The manner in which the PWM wave is modulated by one *O clock by the additional bit becomes clearer in FIG. 11. 1st
In Figure 1, A indicates the timing signal T5, and B indicates the counter 16.
2, and C indicates the output of the flip-flop 166, that is, the flip-flop 166 outputs the timing signal T in the absence of the additional bit signal F5 shown in FIG.

It is reset at the falling edge of Fs, but when Fs is present, it is reset with a delay of one clock of the XO clock shown by E in FIG. Thus, each additional bit modifies the PWM wave.

I believe that the explanation of the embodiments above has been understood, but various modifications can be made to the implementation of the present invention, and there is no need to implement it in practice.

[Brief explanation of the drawing]

Figure 1 is a schematic block diagram showing a conventional servo circuit.
Figure 2 is an operational waveform diagram of the circuit in Figure 1, Figure 3 is a waveform diagram to explain the operation of a general digital error detector, and Figure 4 is a phase diagram to explain the details of the present invention. 5 and 6 are block diagrams of a digital servo circuit according to an embodiment of the present invention, FIGS. 7 and 8 are operational waveform diagrams of this embodiment, and FIG. 9 is an illustration of a digital servo circuit according to an embodiment of the present invention. A block diagram showing the embodiment, and FIGS. 10 and 11 are timing charts for explaining its operation. In the figure, 66 is the speed loop buffer counter, and 7o is PW.
M generation flip-flop; 78 is a speed detection counter;
145 and 146 are 64-decimal counters, 147 is a latch circuit, and 148 is a hexadecimal counter. Patent Applicant Sony Corporation Agent Patent Attorney Nagai 1) Mibe Takeshi 3 Figure 4

Claims (1)

[Claims] A servo circuit characterized in that a feedback period of an output error signal of an error detector of a digital servo circuit is divided into sufficiently large blocks, and pulse width modulation for one bit is performed for each block.