JPH02302178A - Id detection circuit - Google Patents

Abstract

PURPOSE:To constitute the circuit without use of any external capacitor and to attain an inexpensive device by using a D flip-flop in an electronic still camera system so as to detect a difference of a DC non signal level between color difference signals R-Y and B-Y. CONSTITUTION:A clamped color difference signal 'b' is amplified while keeping a clamp level E with a signal amplifier 3 to increase a DC level difference of the color difference signal 'b'. The color difference signal 'b' whose DC level difference is largely emphasized is subject to waveform shaping with a threshold level to output an output waveform 'c' of a voltage comparator 4. A color difference signal 'c' in which not only a level difference of a color difference non-signal level but also a signal component is subject to waveform shape is inputted to a data input of a D flip-flop 7 and a clamp pulse 'a' is inputted as a clock pulse to the D flip-flop to fetch only a high or a low DC level being a non signal level of the color difference signal 'c' subject to waveform shaping and an output is obtained from a Q output of the D flip-flop to output an ID pulse 'd' from an output terminal 8.

Description

Detailed Description of the Invention [Industrial Application Field] This invention is an electronic still camera system in which color difference signals necessary for separating R-Y and B-Y line-sequential color difference signals and converting them into reverse line-sequential The present invention relates to a detection circuit that detects a difference between the L) and C potentials of a signal at a no-signal level.

[Conventional technology]

FIG. 5 is a circuit diagram of a conventional ID detection circuit.

In the figure, (ri) is the input terminal of the line-sequential color difference signal of the ID detection circuit, (2) is the manual clamp circuit that clamps the input color difference signal to a constant potential, (3) is the signal amplifier, αq is the sample hold circuit, and αυ is the The hold capacitor of the sample and hold circuit OQ, (4) is the voltage comparator, (5) is the constant voltage source that becomes the hearing pressure of the voltage comparator (4), and (6) is the input of the clamp pulse (burst flag pulse) terminal, (
8) is an output terminal of the IL) pulse.

FIG. 6 is a timing chart of input and output waveforms of the ID detection circuit of FIG. 5. a is input from the clamp pulse input terminal (6). Clamp pulse (burst flag pulse; hereinafter referred to as clamp pulse), b is a color difference signal in which R-Y and B-Y are line-sequentially processed, and Vxo is a no-signal level for distinguishing R-Y and B-Y. e is the output waveform of the sample-and-hold circuit αQ, and d is the output waveform after VID detection (ID pulse; hereinafter referred to as ID pulse).

Next, the operation will be explained. When a line-sequential color difference signal (hereinafter referred to as a color difference signal) is input from the input terminal (1), the input clamp circuit (2) changes the no-signal level of the color difference signal to a constant voltage source at the timing of the clamp pulse a. (The clamped color difference signal is clamped to the potential E of 5, and the signal is amplified by the signal amplifier (3) while maintaining the potential E, increasing the DC potential difference VID of the color difference signal.V
By sampling and holding the color difference signal with greatly emphasized xb at the timing of clamp pulse a in the sample and hold circuit, the voltage value of the color difference signal at no signal level is sampled and held on the hold capacitor Q. ,
Remove the signal component of the color difference signal. Here, the amplitude value VID2 of the output waveform e from the sample-and-hold circuit α is as follows, where A is the amplification factor of the signal amplifier (3), VID2 = A・
VID holds true.

Next, the waveform is shaped by a voltage comparator (4) having an output waveform e8 and a listening voltage E, and an LD pulse d is outputted from an output terminal (8).

[Problem to be solved by the invention]

Since the conventional Il) detection circuit is configured as described above, a hold capacitor is required in the sample and hold circuit.

Further, in the case of a semiconductor integrated circuit, an external terminal and an external element are required for a hold capacitor.

This invention was made to solve the above-mentioned problems.In the ID detection circuit, the hold capacitor is eliminated, and in the case of a semiconductor integrated circuit, the ID detection circuit is created with the number of external capacitors and external terminals reduced. The purpose is to obtain.

(Means for Solving the Problems) The ID detection circuit according to the present invention uses a D flip-flop to detect the difference in the no-signal level of the color difference signal RY and BY signal by about LICwlL. This is what I did.

[Effect]

In the ID detection circuit of this invention, the ID pulse is not a pulse that detects the potential difference between the R-Y and B-Y signals of the color difference signal, but a pulse that determines only whether the no-signal level is ")liTl" or "Low". Kotomari, 1ζ so that the D flip-flop determines the difference of about DC?llj of the color difference signal as u Hit'"Low" at the timing of the clamp pulse.
act.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
Figure 2 is a circuit diagram of the detection circuit, Figure 2 is a timing diagram of the input/output waveforms of the ID detection circuit in Figure 1, Figures 3 and 4 are
The figure is a circuit diagram of an ID detection circuit according to another embodiment of the invention.

In the figure, (1) to (tl, (8)) are the same as those shown in the conventional example of FIG. 5, so their explanation will be omitted. (7)
is a D-flip-flop.

a is the clamp pulse input from the crank pulse input terminals (1j, l, b is the color difference signal in which the R-Y and B-Y signals are line-sequential), (9) is the threshold of the voltage comparator (4) The threshold N ratio, VID, for the color difference of voltage E and other '\jb is l<-
Nothing to distinguish between Y and B-Y (No. 8 level 'DCv)
The difference in position t, C is the voltage comparator (current output waveform, d is the above V
Output waveform after ID detection (1:D pulsen).

Next, the operation will be explained. When a color difference signal comes in from the input terminal (1), the input clamp circuit (2) clamps the no-signal level of the color difference No. 4N (1) to the clamp potential E at the timing of the clamp pulse a, and the clamped color difference The signal S is amplified by the signal amplifier (3) while maintaining the clamp potential E, thereby increasing the DC@potential difference VID of the color difference signal S. Vto is big! The @I-adjusted color difference signal S is waveform-shaped by a voltage comparator (4) using a signal value voltage (9), and an output waveform C from the voltage comparator (4) is output. The color difference signal C whose waveform has been shaped not only the potential difference VID at the no-signal level of the color difference but also the signal components is input to the data of the D-flip-flop (7), and the clamp pulse a is used as the clock pulse of the D-flip-flop (7). By inputting the data, only the 'Hi' or 'L OIA' of the DC potential difference at the no-signal level of the waveform-shaped color difference signal C is taken in as data and output from the (output) of the D flip-flop (7). Output ID pulse d with Fukuko (8
) is output.

In the above embodiment, the voltage comparator (4) and the signal amplifier (3) are used to shape the waveform of the color difference signal. If the waveform can be shaped only by the signal amplifier (4), the configuration shown in Fig. 3 may be used. 1 Increase the width ratio A,
The DC position difference VID2 of the color difference signal is a D flip-flop (there is sufficient margin for the U value voltage of the power, IT).
If it is possible to determine whether the signal is + or "Low", the single pressure comparator (4) for waveform shaping is not necessary. By providing the signal amplifier (3) with a limiter function, the configuration shown in FIG. 4 may be adopted, and the same effects as in the above embodiment can be achieved.

〔Effect of the invention〕

As described above, according to the present invention, 11) Since the detection circuit is configured without using an external capacitor, the device can be made at a low cost, and even in the case of a semiconductor M path, an external terminal for an external capacitor can be used. Since this is no longer necessary, it has the effect of being able to be constructed at low cost.

[Brief explanation of the drawing]

FIG. 1 shows an ID detection circuit according to an embodiment of the present invention.
-Circuit diagram; FIG. 2 is a timing diagram showing input and output signals of the circuit of FIG. 1; FIGS. 3 and 4 are circuit diagrams of an ID detection circuit according to an embodiment of the present invention; FIG. A circuit diagram of a conventional ID detection circuit, FIG. 6 is a timing diagram of input/output signals of the conventional ID detection circuit. Fifth in the figure, (1) is the input terminal, (2) is the input clamp circuit, (3) is the signal amplifier, (4) is the voltage comparator, (
5) is a constant voltage source, (from June, lamp pulse input terminal, (
7) is a D-flip-flop, (8) is an output terminal, (9
) is the μs value voltage. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] It consists of an input clamp circuit that operates with a clamp pulse (burst flag pulse), a signal amplifier, a voltage comparator that has the clamp voltage of the input clamp circuit as a threshold, and a D flip-flop, and uses the output of the voltage comparator as data. An ID detection circuit characterized in that a D flip-flop is operated using the clamp pulse (burst flag pulse) as a clock.