JPH02302190A - Horizontal synchronizing circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is a lock generation circuit that is necessary for equipment that handles video signals, such as television receivers and VCRs, and in particular for equipment that converts video chroma synchronization circuits into digital signal processing. The present invention relates to a horizontal synchronization circuit having a PLL circuit that generates a clock locked to a horizontal synchronization signal.

2. Description of the Related Art In recent years, equipment that handles video signals has been increasingly digitized. This movement has also spread to consumer products such as television receivers and VCRs.

This is expected not only to reduce the number of parts and improve reliability, but also to make the video chroma synchronization circuit easier to apply to HDTVs due to digitalization (this is a promising technology).

By the way, when video chroma circuits are converted to digital signal processing, a system clock is naturally required to drive those circuits, but in order to effectively process data with a limited sampling frequency and number of bits, a system clock is required. It is convenient to lock on signals with strong correlation.
Currently, two types of clocks are being put into practical use as clock regeneration methods: burst lock systems and line lock systems. Both have advantages and disadvantages, and there is no conclusion as to which method is better. . There are two methods: analog playback and digital signal processing. Although clock regeneration using digital signal processing is a method that will lead to the future,
In the case of a line lock system, various problems occur that necessitate a fundamentally different method, unlike the relatively well-established synchronous playback using an analog method.

An example of the horizontal synchronization circuit of the conventional line lock system using digital signal processing as described above will be described below with reference to the drawings.

FIG. 2 shows a block diagram of an example of a conventional horizontal synchronization circuit. In FIG. 2, 21 is an AD converter that inputs a composite video signal and converts it into a digital code.

22 is a low-pass filter that receives the output of the AD converter 21, passes horizontal frequency components, and blocks subcarrier frequency components. 23 is the above low-pass filter 2
This is a pedestal level detection circuit which inputs the output of 2 and detects the pedestal level. Reference numeral 24 denotes a synchronization signal separation circuit that extracts a synchronization signal by subtracting the output of the low-pass filter 22 from the output of the pedestal level detection circuit 23 and setting the negative number to O. Reference numeral 25 denotes a slice level detection circuit which inputs the output of the synchronization signal separation circuit 24, detects the peak value of the synchronization signal, and outputs a fixed ratio from that value. 26 is a comparator which takes the difference between the output of the synchronization signal separation circuit 24 and the output of the slice level detection circuit 25. Reference numeral 27 denotes an edge detection circuit which receives the output of the comparator 26 and detects the falling edge of the horizontal synchronizing signal. A phase comparator 28 compares the phase between the output of the edge detection circuit 27 and the horizontal pulse generated by the frequency divider. A loop filter 29 inputs the output of the phase comparator 28 and cuts off high-frequency components. 30
is a VCO which inputs the output of the loop filter 29 and controls the oscillation frequency based on data. 31 is the above V
This is a frequency divider that inputs the clock generated by the CO 30 and divides the frequency by 1/N, and outputs the horizontal pulse obtained by frequency division to the phase comparator 28.

The operation of the horizontal synchronization circuit configured as described above will be explained below.

First, the composite video signal is input to the AD converter 21. The composite video signal digitally encoded by the AD converter 21 is input to a low-pass filter 22, which passes horizontal frequency components, blocks subcarrier frequency components, and suppresses noise components and subcarrier components. The pedestal level detection circuit 23 detects the pedestal level from the output of the low-pass filter 22. Next, in the synchronization signal separation circuit 24, the output of the low-pass filter 22 is subtracted from the output of the pedestal level detection circuit 23 to make the negative number zero, thereby extracting only the synchronization signal. Next, in order to extract the horizontal synchronization signal component from the synchronization signal, the slice level detection circuit 25 inputs the output of the synchronization signal separation circuit 24, detects the peak value of the synchronization signal, and multiplies that value by a certain percentage. Output the value. Generally, the ratio should be 1/2, but if whisker-like noise is superimposed on the synchronous component such as a VCR signal, it may be better to adaptively change the ratio and slice from the tip. There is also. A comparator 26 takes the difference between the output of the synchronization signal separation circuit 24 and the slice level detection circuit 25, and converts the synchronization horizontal synchronization signal into 1-bit data. The output of the comparator 26 is input to an edge detection circuit 27 to detect the falling edge of the horizontal synchronization signal. Phase comparator 2
In step 8, as an example of 0 phase detection, the phase of the output of the edge detection circuit 27 is compared with the horizontal pulse generated by the frequency divider, the phase is determined by launching the data generated by the frequency divider at the timing when an edge is rising. The output of the 0 phase comparison 28, which allows comparison, is input to the loop filter 29,
Cuts off high-frequency components and converts the output of the loop filter 29 into a VCO
30, and the oscillation frequency is controlled by the data.

The clock generated by the VCO 30 is input to a frequency divider 31 and divided into 1/N. The horizontal pulse obtained by frequency division is outputted to the phase comparator 28, so that the horizontal PLL circuit operates to generate a line-locked clock.

Problems to be Solved by the Invention However, with the above configuration, if the upper part of the screen curves due to the skew caused by head switching that occurs just before the vertical signal when playing a VCR tape, the loop filter is used to prevent the skew caused by fast forwarding. Since there is only one type of time constant, it is difficult to respond well. If the time constant is made lighter, good results can be obtained with respect to skew, but jitter characteristics become worse, and horizontal characteristics in weak electric fields become worse.

Conversely, if the time constant is made heavier, the jitter characteristics will improve, but the skew characteristics will worsen and the screen will be more likely to curve when a skew signal is input.

In view of the above problems, the present invention provides a horizontal synchronization circuit whose jitter characteristics and skew characteristics are always stable even in a weak electric field or during VCR tape playback.

Means for Solving the Problems In order to solve the above problems, the horizontal synchronization circuit of the present invention includes an AD converter that inputs a composite video signal and converts it into a digital code, and an output of the AD converter, and horizontal frequency components are A low-pass filter that passes through and blocks subcarrier frequency components, a pedestal level detection circuit that receives the output of the low-pass filter and detects the pedestal level, and subtracts the output of the low-pass filter from the output of the pedestal level detection circuit to obtain a negative number. By setting O, a sync signal separation circuit extracts the sync signal, and a slice level detection circuit receives the output of the sync signal separation circuit, detects the peak value of the sync signal, and outputs a fixed ratio from that value. , a comparator that takes the difference between the output of the synchronization signal separation circuit and the output of the slice level detection circuit; an edge detection circuit that receives the output of the comparator and detects a falling edge of the horizontal synchronization signal; A phase comparator that compares the phase between the output of the circuit and the horizontal pulse output from the frequency divider, and a loop filter that inputs the output of the phase comparator, cuts off high-frequency components, and whose time constant is switched by a control signal. , input the output of the above loop filter, detect its variation, and if the variation is small from 0, increase the time constant of the loop filter, and if the variation from O is large, decrease the time constant of the loop filter. a skew detection circuit configured to send a control signal to a control terminal of the loop filter, and a CO inputting the output of the loop filter to control the oscillation frequency based on data;
The device is equipped with a frequency divider that inputs the clock generated by the CO and outputs a horizontal pulse whose frequency has been divided by N to the phase comparator.

Effect of the Invention With the above-described configuration, the present invention reduces the time constant of the loop filter to quickly converge when the skew is large, and increases the time constant of the loop filter to quickly converge the PLL loop when there is no or little skew. It becomes possible to achieve stabilization.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 shows a block diagram of a horizontal synchronization circuit in one embodiment of the present invention. In Fig. 1, 1 is an AD converter that inputs a composite video signal and converts it into a digital code, 2 is a low-pass filter that inputs the output of AD converter 1, passes horizontal frequency components and blocks subcarrier frequency components, and 3 A pedestal level detection circuit inputs the output of the low-pass filter 2 and detects the pedestal level, and 4 is a synchronization signal that extracts a synchronization signal by subtracting the output of the low-pass filter from the output of the pedestal level detection circuit 3 and setting it as a negative number O. Separation circuit, 5 is a slice level detection circuit which inputs the output of the synchronization signal separation circuit 4, detects the peak value of the synchronization signal, and outputs a certain ratio from that value; 6 is the output of the synchronization signal separation circuit 4; and the output of the slice level detection circuit 5; 7 is an edge detection circuit which receives the output of the comparator 6 and detects the falling edge of the horizontal synchronization signal; 8 is an edge detection circuit of the edge detection circuit 7; The phase comparator 9, which compares the phase of the output with the horizontal pulse output from the frequency divider, inputs the output of the phase comparator 8 and cuts off the high-frequency components. I7 Loop filter whose time constant can be switched depending on the call signal, I
O inputs the output of the loop filter 9, detects the variation, and if the variation is smaller than O, the loop filter 9
11 is the loop filter 9; 11 is the loop filter 9; The VCO 112, which inputs the output of
This is a frequency divider that outputs the horizontal pulse whose frequency can be divided into 1 to 1 to the phase comparator.

The operation of the horizontal synchronization circuit configured as described above will be explained below.

The composite video signal is input to an AD converter l and converted into digital code. A digitally encoded composite video signal is input to a low-pass filter 2, which passes horizontal frequency components and blocks subcarrier frequency components. The output of the low-pass filter 2 is input to the pedestal level detection circuit 3, and the 0-order synchronization signal separation circuit 4 detects the pedestal level.
A slice level detection circuit 5 inputs the output of the synchronization signal separation circuit 4 and extracts a synchronization signal by subtracting the output of the low-pass filter from the pedestal level detected by the pedestal level detection circuit 3. Detects the peak value of the wave and outputs a certain percentage of that value. A comparator 6 calculates the difference between the output of the synchronization signal separation circuit 4 and the output of the slice level detection circuit 5,
Convert to 1-bit horizontal synchronization signal. The horizontal synchronization signal converted to 1 bit is input to an edge detection circuit 7, and a falling edge of the horizontal synchronization signal is detected. Next, the phase comparator 8 compares the phase between the output of the edge detection circuit 7 and the horizontal pulse output from the frequency divider.

The output data of the phase comparator 8 is input to a loop filter 9, high-frequency components are cut off, and an appropriate response time and damping factor of the PLL loop are set. The output of the loop filter 9 is inputted to the Schiera detection circuit 10, and its fluctuation is detected. If the fluctuation is smaller than 0, the time constant of the loop filter 9 is increased, and if the fluctuation is large than 0, the time constant of the loop filter 9 is increased. A control signal is sent to the control terminal of the loop filter 9 so as to reduce the time constant. The output of the loop filter 9 is input to the VCO II, and the oscillation frequency is controlled by the data. The clock generated by the VCO II is input to the frequency divider 12, and the horizontal pulse obtained by dividing the frequency by 1/N is output to the phase comparator 8.

As described above, the PLL loop operates in response to the horizontal synchronizing signal, and at the same time, the time constant of the loop filter is automatically switched in accordance with the amount of skew.

Next, a more specific example of the Schiera detection circuit will be described. FIG. 3 is a block diagram of an example of a skew detection circuit, where 41 is a decoder that inputs the output of the loop filter, and outputs low when the input data is within a set arbitrary range, and when it is outside the range. If so, output high. The loop filter 9 increases the time constant when the control terminal is set to low, and shortens the time constant when set to high. The above operation makes it possible to automatically switch the time constant.

Note that since the temporal resolution of the phase comparator described above is one clock precision, clock jitter occurs for one clock or more. This problem can be solved by using an integral phase comparator in combination to obtain an accuracy of one clock or less, and switching between when the phase error is small and when it is large.

Next, an example of this integral phase comparator will be described. Fourth
The figure is a block diagram of an example of an integral phase comparator, 51
52 is an adder that adds the data string of positive horizontal synchronizing pulses outputted from the synchronizing signal separation circuit 4 and the other input signal data string, and 52 is the output of the adder 51 and the other input signal data string. A multiplexer 53 performs switching between the two using an integral pulse inputted to a control terminal, and stores the output signals of the multiplexer 52 using the system clock, and sends the output to the other input of the adder 51 and the other input of the multiplexer. The first with a clear input terminal connected
The latch 54 is a second latch that stores the output of the first latch 53 in horizontal rate pulses.

The operation of the integral phase comparator configured as above will be described below.

The horizontal synchronizing pulse of positive polarity output from the synchronizing signal separation circuit 4 is integrated by an accumulator composed of an adder 51, a multiplexer 52, and a first latch 53 during the on period of the integral pulse, and during the on period of the integral pulse. The area of the horizontal sync pulse is detected. This result shows that the latch pulse generated at the trailing edge of the integral pulse causes the second latch 5 to
4 is stored.

This latch pulse is also input to the clear input of the first latch 53 to clear the first latch 53 and prepare for the next integration. A timing diagram of the integration is shown in FIG. 5. When the horizontal synchronizing pulse is delayed, the integration amount decreases to the minimum O.

As the horizontal pulse moves forward, the integrated amount increases, and when only the horizontal synchronizing pulse portion is integrated, the integrated amount becomes maximum. Therefore, if the output data of the second latch 54 is corrected so that the output data of this integral phase comparator becomes O when the front edge of the horizontal synchronizing pulse is multiplied by X at the timing shown in FIG. It becomes possible to perform phase comparison.

Note that the linear output range of this integral type phase comparator is only the range in which the width of the integral pulse spans the rising edge of the horizontal synchronizing pulse, so if the phase is out of this range, the edge signal described above is automatically applied. It is necessary to switch to using a detection type phase comparator.

Effects of the Invention As described above, according to the present invention, an AD converter inputs a composite video signal and converts it into a digital code, and the output of the AD converter is input, horizontal frequency components are passed through and subcarrier frequency components are blocked. A low-pass filter, a pedestal level detection circuit that inputs the output of the low-pass filter and detects the pedestal level, and a synchronization signal is extracted by subtracting the output of the low-pass filter from the output of the pedestal level detection circuit and setting the negative number to 0. a sync signal separation circuit, a slice level detection circuit that receives the output of the sync signal separation circuit, detects the peak value of the sync signal, and outputs a certain percentage from that value; A comparator that takes the difference between the output of the slice level detection circuit, an edge detection circuit that receives the output of the comparator and detects the falling edge of the horizontal synchronization signal, and a horizontal difference between the output of the edge detection circuit and the output of the frequency divider. a phase comparison il that performs phase comparison with the pulse;
a loop filter that inputs the output of the phase comparator, cuts off high-frequency components, and whose time constant is switched by a control signal;
Input the output of the above loop filter, detect its fluctuation, and if the fluctuation from 0 is small, increase the time constant of the loop filter, and if the fluctuation from 0 is large, reduce the time constant of the loop filter. A skew detection circuit that sends a control signal to a control terminal, a VCO that inputs the output of the loop filter and controls the oscillation frequency based on data, and a clock generated by the VCO that inputs and divides the frequency by 1/N. By providing a frequency divider that outputs the resulting horizontal pulse to the phase comparator, it is possible to generate a stable line-locked clock with good jitter and skew characteristics even when receiving non-standard signals or weak electric fields. A horizontal synchronization circuit can be constructed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a horizontal synchronization circuit in an embodiment of the present invention, FIG. 2 is a block diagram of a horizontal synchronization circuit in a conventional embodiment, FIG. 3 is a block diagram of an example of a skew detection circuit, and FIG. The figure is a block diagram of an integral phase comparator, the fifth
The figure is a timing diagram illustrating an integral phase comparator. 1...AD converter, 2...Low pass filter, 3...Pedestal level detection circuit, 4...Synchronization signal separation circuit, 5...・Slice level detection circuit, 6... comparator,
7. Old... Engineering/Nji detection times! , 8... Phase comparator, 9... Loop filter, 10...
Skew detection circuit, 1! ...VCO112...
...Frequency divider, 41...Decoder. Name of agent: Patent attorney Shigetaka Awano (1 person) Figure 1 Figure 2 Figure 3 Figure 4rM Figure 5

Claims (3)

[Claims] (1) An AD converter that inputs a composite video signal and converts it into a digital code, a low-pass filter that inputs the output signal of the AD converter, passes horizontal frequency components, and blocks subcarrier frequency components; a pedestal level detection circuit that inputs an output signal and detects a pedestal level; and a synchronization signal separation circuit that extracts a synchronization signal by subtracting the output signal of the low-pass filter from the output signal of the pedestal level detection circuit and setting the negative number to 0. and a slice level detection circuit that inputs the output signal of the synchronization signal separation circuit, detects the peak value of the synchronization signal, and outputs a certain ratio from that value, and outputs the output signal of the synchronization signal separation circuit and the slice level. A comparator that takes the difference between the output signal of the detection circuit, an edge detection circuit that receives the output signal of the comparator and detects the falling edge of the horizontal synchronization signal, and the output signal of the edge detection circuit and the output of the frequency divider. a phase comparator that performs a phase comparison with the horizontal pulse that is generated; a loop filter that inputs the output signal of the phase comparator, cuts off high-frequency components, and whose time constant is switched by a control signal; A control signal is sent to the control terminal of the loop filter so that the time constant of the loop filter is increased if the fluctuation is small from 0, and the time constant of the loop filter is decreased if the fluctuation is large from 0. a skew detection circuit configured to send out
Input O and the clock generated by the above VCO, and 1/N
A horizontal synchronization circuit comprising a frequency divider that outputs a horizontal pulse frequency-divided into the phase comparator to the phase comparator. (2) An integrating type phase comparator is provided in parallel with the above phase comparator, and when the phase error is large, the output data of the above phase comparator is selected, and when the phase error is small, the output data of the integrating type phase comparator is selected. A horizontal synchronizing circuit according to claim (1), wherein data is selected. (3) The horizontal synchronization circuit according to claim (1), wherein the skew detection circuit is configured to detect the amount of skew by decoding output data of a loop filter.