JPH0319590A - Horizontal synchronizing circuit - Google Patents

Abstract

PURPOSE:To improve noise elimination effect and to attain stable horizontal synchronization reproduction even at a weak electric field by switching a limiter width of a limiter limiting a fluctuation of data outputted from a phase comparator depending on at the weak electric field signal reception and at the normal electric field signal reception and making the limiter width narrow at a weak electric field. CONSTITUTION:An output of a phase comparator 8 comparing the phase of an output of an edge detection circuit 7 and the phase of a horizontal pulse outputted from a frequency divider is inputted to a limiter 9, which outputs a maximum value of the setting range when a level exceeding the set range is inputted to eliminate noise component. Moreover, a weak electric field signal detection circuit 13 detects a weak electric field, and outputs a control signal for the limiter 9 to make the limiter width of the limiter 9 narrow in the case of the weak electric field. Thus, the limiter level is switched depending on at the weak electric field signal reception and at the normal electric field signal reception and the limiter range is made narrow at the weak electric field to improve noise eliminating effect thereby attaining stable horizontal synchronization reproduction even at the weak electric field.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a clock generation circuit necessary for equipment that handles video signals such as television receivers and VCRs, especially equipment that converts video chroma synchronization circuits into digital signal processing. This relates to a horizontal synchronization circuit having a PLL circuit that generates a clock locked to a horizontal synchronization signal. Background of the Invention In recent years, equipment that handles video signals has become increasingly digital. This movement is also extending to consumer equipment such as television receivers and VCRs. This technology is expected to not only reduce the number of parts and improve reliability, but also make it easier to apply video chroma circuits to HDTVs through digitalization, making it a highly anticipated technology. By the way, when a video chroma circuit is converted to digital signal processing, a system clock is naturally required to drive the circuit, but in order to effectively process data with a limited sampling frequency and number of bits, a system clock is required. It is convenient for the clock to be locked to signals with strong correlation. Currently, two types of clocks are being put into practical use as clock recovery methods: burst lock systems and line lock systems. Both methods have advantages and disadvantages, and there is no conclusion as to which method is better.
There are two methods: analog playback and digital signal processing. Although clock regeneration using digital signal processing is a method that will lead to the future, in the case of a line lock system, unlike the relatively established analog method of synchronous regeneration, a method that is fundamentally different is required. Various problems arise that require action. An example of the horizontal synchronization circuit of the conventional line lock system using digital signal processing as described above will be explained below with reference to the drawings. Figure 2 shows a block diagram of an example of a conventional horizontal synchronization circuit. In FIG. 2, 21 is an AD converter that inputs a composite video signal and converts it into a digital code. 22 is the above AD converter 2
This is a low-pass filter that inputs the output of 1 and passes the horizontal frequency component and blocks the subcarrier frequency component. 23 is a pedestal level detection circuit which receives the output of the low-pass filter 22 and detects the pedestal level. 24
is a synchronization signal separation circuit which extracts a synchronization signal by subtracting the output of the low-pass filter 22 from the output of the pedestal level detection circuit 23 and setting the negative number to O. 25
is a slice level detection circuit which inputs the output of the synchronization signal separation circuit 24, detects the peak value of the synchronization signal, and outputs a fixed ratio from that value. 26 is a comparator which takes the difference between the output of the synchronization signal separation circuit 24 and the output of the slice level detection circuit 25. 27 is an edge detection circuit which receives the output of the comparator 26 and detects the edge of the horizontal synchronization signal. 28 is a phase comparator that compares the phase between the output of the edge detection circuit 27 and the horizontal pulse generated by the frequency divider. 29 is the phase comparator 28
This is a loop filter that inputs the output of and cuts out high-frequency components. 30 is a VCO which receives the output of the loop filter 29 and controls the oscillation frequency based on the data. 31 is a frequency divider which inputs the clock generated by the vC○ 30 and divides the frequency into 1/N, and outputs the horizontal pulse obtained by dividing the clock to the phase comparator 28. The operation of the horizontal synchronization circuit configured as described above will be explained below. First, the composite video signal is input to the AD converter 21.The composite video signal digitally encoded by the AD converter 2l is input to the low-pass filter 22, where the horizontal frequency component is passed, the subcarrier frequency component is blocked, and noise or Detection and suppression of subcarrier weight. Next, the synchronization signal separation circuit 24 subtracts the output of the low-pass filter 22 from the output of the pedestal level detection circuit 23 to set the negative number to 0, thereby extracting only the synchronization signal. Next, in order to extract the horizontal synchronization signal power from the synchronization signal, the slice level detection circuit 25 inputs the output of the synchronization signal separation circuit 24, detects the peak value of the synchronization signal, and multiplies that value by a certain ratio. Outputs . Generally, the ratio is 1/2
However, if whisker-like noise is superimposed on the same signal, such as a VCR signal, it may be better to adaptively change the ratio and slice from the tip. Converter 2
6, the difference between the output of the synchronization signal separation circuit 24 and the output of the slice level detection circuit 25 is taken, and the horizontal synchronization signal is converted into 1-bit data. Edge detection circuit 27
The output of the comparator 26 is input to the input terminal 26 to detect the edge of the horizontal synchronization signal. In the phase comparator 28: The phase of the output of the edge detection circuit 27 and the horizontal pulse generated by the frequency divider is compared. As an example of phase detection, phase comparison is possible by latching the data generated by a frequency divider at the timing of a rising edge. The output of the phase comparator 28 is input to a loop filter 29 to cut off high-frequency signals,
The output of the loop filter 29 is input to the VCO 30, and the oscillation frequency is controlled by the data. The clock signal generated by the above ■C○30 is input to the frequency divider 31 and divided into 1/N. The horizontal pulse obtained by frequency division is outputted to the phase comparator 28, so that the horizontal PLL circuit operates to generate line lock. Problems to be Solved by the Invention However, in the above structure, since a broadcast signal is being received even when a weak electric field signal is being received, the output of the phase comparator should not fluctuate, but due to noise. The data output from the phase comparator fluctuates greatly due to superimposition. A limiter characteristic is applied to the output of the phase comparator so that the data does not fluctuate beyond a certain range, but in consideration of the VCR playback signal, this limiter characteristic must have a slope width of several percent or more. However, when a weak electric field signal is received, this limiter width is too wide and cannot sufficiently remove the noise caused by the weak electric field.Therefore, if left as is, there is a problem in performing phase comparison with poor snaking characteristics. In view of the above problems, the present invention provides a horizontal synchronization circuit that performs phase comparison with stability and high noise removal ability even when receiving weak electric field signals. Means for Solving the Problems In order to solve the above problems, the horizontal synchronization circuit of the present invention includes an AD converter that inputs a composite video signal and converts it into a digital code, and an AD converter that inputs the output of the AD converter and passes horizontal frequency components. a low-pass filter that cuts off some of the subcarrier frequencies, a pedestal level detection circuit that receives the output of the low-low filter and detects the pedestal level, and subtracts the output of the low-pass filter from the output of the pedestal level detection circuit to obtain a negative number. a sync signal separation circuit that extracts a sync signal by extracting the sync signal; a slice level detection circuit that inputs the output of the sync signal separation circuit, detects the peak value of the sync signal, and outputs a certain percentage from that value; a comparator that takes the difference between the output of the synchronization signal separation circuit and the output of the slice level detection circuit; an edge detection circuit that receives the output of the comparator and detects the edge of the horizontal synchronization signal; There is a phase comparator that compares the phase with the horizontal pulse output by the frequency generator, and the output of the phase comparator is input, and if a value exceeding the set range is input, the maximum value within the set range is output. At the same time, there is a limiter whose set value can be changed by an external control signal, a loop filter that inputs the output of the limiter and cuts off high-frequency components, and a loop filter that inputs the output of the loop filter and adjusts the oscillation frequency according to the data. ■C○ which controls the gate, a frequency divider which inputs the clock generated by the above VC○ and outputs the horizontal pulse which can be divided into 1/N to the above phase comparator, and a frequency divider which detects a weak electric field and outputs it to the above phase comparator. In the case of an electric field, it has the power of a weak electric field signal detection circuit that outputs a control signal for the limiter so as to narrow the limiter's limiter width. Effect of the present invention With the above-described configuration, the limiter width ξ7 which limits fluctuations in the data output from the phase comparator is switched between when receiving a weak electric field signal and when receiving a normal electric field signal, and narrowing the limiter width when the electric field is weak. This increases the noise removal effect and enables stable horizontal synchronized playback even in weak electric fields. EXAMPLE An example of the present invention will be described below with reference to the drawings. FIG. 1 shows a block diagram of a horizontal synchronization circuit in one embodiment of the present invention. In FIG. 1, ■ is an AD converter that inputs a composite video signal and converts it into a digital code; 2 is a low-pass filter that inputs the output of the AD converter 1, passes the horizontal frequency signal, and cuts off the subcarrier frequency; 3 is a pedestal level detection circuit that receives the output of the low-pass filter 2 and detects the pedestal level; 4 is a synchronizing signal by subtracting the output of the low-pass filter 2 from the output of the pedestal level detection circuit 3 and setting the negative number to 0; 5 is a slice level detection circuit which inputs the output of the periodic signal separation circuit 4, detects the peak value of the synchronization signal, and outputs a fixed ratio from that value; 6 is the synchronization signal separation circuit described above. 7 is an edge detection circuit that receives the output of the comparator 6 and detects the edge of the horizontal synchronization signal; 8 is the output of the edge detection circuit 7; A phase comparator 9 performs a phase comparison between the horizontal pulse output from the frequency divider, and 9 inputs the output of the phase comparator 8. If a value exceeding the set range is input, the maximum value of the set range is input. 10 is a loop filter that inputs the output of the limiter 9 and cuts off the high frequency band, and 11 is the loop filter described above. vCO which inputs the output of IO and controls the oscillation frequency by data; 2 is a frequency divider which inputs the clock signal generated by VCOII and outputs the horizontal pulse whose frequency has been divided by N to the phase comparator 8; A weak electric field detection circuit 13 detects a weak electric field and outputs a control signal for the limiter 9 so as to narrow the limiter width of the limiter 9 if the electric field is weak. The operation of the horizontal synchronization circuit horizontally arranged as described above will be explained below. The composite video signal is input to AD converter 1 and converted into digital code.
The digitally encoded composite video signal is filtered through a robust filter 2.
The horizontal frequency component is passed through and the subcarrier frequency component is blocked. The output of the low-pass filter 2 is input to the pedestal level detection circuit 3 to detect the pedestal level. Next, in the synchronization signal separation circuit 4, the output of the single pass filter is subtracted from the pedestal level detected by the pedestal level detection circuit 3, and the negative number is set to O, thereby extracting the synchronization signal. The slice level detection circuit 5 inputs the output of the synchronization signal separation circuit 4, detects the peak value of the synchronization signal, and outputs a certain percentage from that value. A converter 6 takes the difference between the output of the synchronization signal separation circuit 4 and the output of the slice level detection circuit 5 and converts it into a 1-bit horizontal synchronization signal. The output of the comparator 6, which has become this 1-bit horizontal synchronization signal, is input to the edge detection circuit 7,
Detect the edge of the horizontal synchronization signal. Next, a phase comparator 8 compares the phase between the output of the edge detection circuit 7 and the horizontal pulse output from the frequency divider. The output of the phase comparator 8 is inputted to the remisota 9, and if a value exceeding the set range is input, the maximum value within the set range is output. This is a necessary function to remove noise components and limit the frequency change width of the PLL. The setting value can be changed using an external control signal. The output of the limiter 9 is input to the curve filter 10 to cut off the high-frequency components and PL
Set the required response of L. The output of the loop filter IO is input to VCOII, and the oscillation frequency is controlled by the data. The clock generated by the VC○11 is input to the frequency divider l2, and the horizontal pulse whose frequency has been divided by N is output to the phase comparator 8. Also, the weak electric field signal detection circuit 13
detects a weak electric field, and if it is a weak electric field, outputs a control signal for the upper vine 9 so as to narrow the slope ξ width of the liminter 9. As described above, the limiter width that limits fluctuations in the data output from the phase comparator is switched between when receiving a weak electric field signal and when receiving a normal electric field signal, and by narrowing the width when the electric field is weak, the noise is reduced. This enhances the removal effect and enables stable horizontal synchronized playback even in weak electric fields. Incidentally, since the temporal resolution of the phase comparator described above is one clock precision, clock jitter of one clock or more is generated. This problem can be solved by using an integral phase comparator to obtain accuracy of one clock or less, and switching between when the phase error is small and when it is large. Next, we will discuss an example of this integral phase comparator. FIG. 3 is a block diagram of an example of an integral phase comparator, and 5l is a processor that adds the data string of the positive horizontal synchronizing pulse output from the synchronizing signal separation circuit 4 and the other input signal data string. X unit 52 is a multiplexer that switches between the output of the adder 51 and the other input signal data string using an integral pulse input to a control terminal; 53 stores the output signal of the multiplexer 52 with a system clock and outputs it; A first latch with a clear input terminal is connected to the other input of the adder n51 and the other input of the multiplexer, and 54 is a second latch that stores the output of the first latch 53 in horizontal rate pulses. This is the latch. As mentioned above, fjl7i! The operation of the integrated phase comparator will be explained below. The horizontal synchronizing pulse of positive polarity output from the synchronizing signal separation circuit 4 is integrated by an accumulator composed of an adder 51, a multiplexer 52, and a first latch 53 during the ON period of the integrating pulse.
The area of the horizontal synchronization pulse during the on period of the integral pulse is detected. This result is stored in the second latitude 54 by a latch pulse that occurs in green after the integration pulse. This latch pulse is also input to the clear input of the first latch 53 to clear the first latch 53 and prepare for the next integration. Figure 4 shows the timing diagram for this integration. If the horizontal synchronization pulse is delayed, the total value decreases and reaches a minimum of 0. As the horizontal pulse moves forward, the amount of integration increases, and when only the horizontal sync pulse portion is integrated, the amount of integration becomes maximum. Therefore, the fourth
If the output data of the second latch 54 is corrected so that the output data of this integrating type phase comparator becomes 0 when the leading edge of the horizontal synchronizing pulse is integrated at the timing shown in the figure, phase comparison can be performed. becomes possible. Note that the linear output range of this integral phase comparator is only the range in which the width of the integral pulse spans the rising edge of the horizontal synchronizing pulse, so if the phase is further out of range, the edge described above is automatically detected. It is necessary to switch to using a detection type phase comparator. Next, an example of the weak electric field signal detection circuit explained above will be explained. FIG. 5 is a block diagram of an example of a weak electric field signal detection circuit, and 61 is a first circuit which inputs a 1-bit horizontal synchronization signal output from the edge detection circuit 6 and integrates the number of horizontal synchronization signals during a horizontal period. 62 is a first comparator that compares the data output from the first accumulator 61 with preset data and outputs ON if it is larger; 63 is a first comparator that inputs the output of the first comparator 62; A second accumulator 64 that integrates the number of ONs during a period is a second converter that compares the data output from the second accumulator 63 with preset data and outputs ON if the data is larger. The operation of the weak electric field signal detection circuit that has been neglected as described above will be explained below. 1 output by the edge detection circuit 6
The horizontal synchronization signal, which has become a bit, is sent to the first accumulator 6.
Enter 1. Here, the number of horizontal synchronization signals during one horizontal period is accumulated. If received in a normal electric field, the number of horizontal synchronization signals during one horizontal period is 1. If a weak electric field signal is received, the number of horizontal synchronization signals during one horizontal period will be 1 or more due to the noise contained therein. The first comparator 62 compares it with the set number and if it is larger, it is determined that the electric field is weak at the horizontal rate and outputs ON. Next, the output of the first comparator 62 is input to the second comparator 63, and the number of ON states of the first comparator during the I vertical period is integrated. This number of ons is input to the second converter 64 and compared with a preset number, and if it is larger, it is determined that the electric field is weak at the vertical rate and an on is output to the control terminal of the limiter 9. The operation described above makes it possible to determine whether a weak electric field signal is being received based on the vertical rate by counting the number of horizontal synchronization signals and detecting whether the number is higher than normal. If necessary, it is also possible to add an additional accumulator to this output to increase the time constant. In addition, although an example of counting the number of horizontal synchronization signals is shown as an example of a weak electric field signal detection circuit, the AGC generated in the VIP circuit
It goes without saying that the control terminal of limiter 9 may be controlled by detecting the voltage. Effects of the Invention As described above, according to the present invention, an AD converter inputs a composite video signal and converts it into a digital code, and an output of the AD converter is inputted, horizontal frequency components are passed through, and subcarrier frequency components are blocked. A low-pass filter, a pedestal level detection circuit that receives the output of the low-pass filter and detects the vedestal level, and synchronization that extracts a synchronization signal by subtracting the output of the low-pass filter from the output of the pedestal level detection circuit and setting the negative number to O. a signal separation circuit, a slice level detection circuit that inputs the output of the synchronization signal separation circuit, detects the peak value of the synchronization signal, and outputs a certain ratio from that value; a comparator that takes the difference from the output of the level detection circuit; an edge detection circuit that receives the output of the comparator and detects the edge of the horizontal synchronization signal;
A phase comparator that compares the phase between the output of the edge detection circuit and the horizontal pulse output from the frequency divider, and a phase comparator that inputs the output of the phase comparator and if a value exceeding the set range is input, the set range a limiter configured to output the maximum value of the limiter and whose set value can be changed by an external control signal; a loop filter that inputs the output of the limiter and cuts off high-frequency components; Input the output of the filter and control the oscillation frequency by data v
c○, a frequency divider that inputs the clock generated by the vCO, divides the frequency by 1/N, and outputs the horizontal pulse to the phase comparator, detects a weak electric field, and if the electric field is weak, the above and a weak electric field signal detection circuit that outputs a control Jl signal of the limiter so as to narrow the width of the limiter. By switching the width between when receiving a weak electric field signal and when receiving a normal electric field signal, and narrowing the limiter width for weak electric fields, the noise removal effect is enhanced, and stable horizontal synchronized playback can be performed even in weak electric fields.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a horizontal synchronous circuit according to an embodiment of the present invention, FIG. 2 is a block diagram of a horizontal synchronous circuit according to a conventional embodiment, and FIG. 3 is a block diagram of an integrating phase comparator. ! Figure 44 is a timing diagram for explaining an integral phase comparator, and Figure 5 is a block diagram of an example of a weak electric field signal detection circuit. ■...AD converter, 2...Low pass filter, 3...Pedestal level detection circuit, 4...Synchronization signal separation circuit, 5...・Slice level detection circuit, 6... comparator,
7... Edge detection circuit, 8... Phase comparator, 9... Limiter, 10... Loop filter, 11... ■C ○, l2...
・Frequency divider, 13... Weak electric field signal detection circuit.

Claims (3)

[Claims] (1) An AD converter that inputs a composite video signal and converts it into a digital code, a low-pass filter that inputs the output signal of the AD converter, passes horizontal frequency components, and blocks subcarrier frequency components, and an output signal of the low-pass filter. a pedestal level detection circuit that detects the pedestal level by inputting the pedestal level; a sync signal separation circuit that extracts the sync signal by subtracting the output signal of the low-pass filter from the output signal of the pedestal level detection circuit and setting the negative number to 0; a slice level detection circuit that inputs the output signal of the signal separation circuit, detects the peak value of the synchronization signal, and outputs a certain ratio from that value; an output signal of the synchronization signal separation circuit; and an output signal of the slice level detection circuit. A comparator that calculates the difference between If a value exceeding the set range is input by inputting the output signal of the phase comparator and the output signal of the phase comparator mentioned above, the maximum value of the set range is output, and the set value is output by an external control signal. a loop filter that inputs the output signal of the limiter and cuts off high-frequency components; a VCO that inputs the output signal of the loop filter and controls the oscillation frequency according to data; A frequency divider that inputs the generated clock and outputs the horizontal pulse divided by N to the phase comparator, and a frequency divider that detects a weak electric field and narrows the limiter width of the limiter if the electric field is weak. and a horizontal synchronization circuit consisting of a weak electric field signal detection circuit that outputs a control signal for the limiter. (2) An integral type phase comparator is provided in parallel with the series circuit of the phase comparator and limiter, and when the phase error is large, the output data of the limiter is selected, and when the phase error is small, the integral type phase comparator is used. 2. The horizontal synchronizing circuit according to claim 1, wherein the output data of the horizontal synchronizing circuit is selected. (3) A first accumulator that inputs the 1-bit horizontal synchronization signal output from the edge detection circuit and integrates the number of horizontal synchronization signals during one horizontal period, and the data output from the first accumulator and settings in advance. a first comparator that compares the magnitude with the data and outputs ON if it is larger; a second accumulator that inputs the output of the first comparator and accumulates the number of ON during one vertical period; Claim (1) further comprising a weak electric field signal detection circuit comprising a second comparator that compares the data output from the accumulator with preset data and outputs ON to the control terminal of the limiter if the data is larger. horizontal synchronous circuit.