JPH02302995A - Encoding circuit - Google Patents

Abstract

PURPOSE:To correctly transmit the information of an output inhibited input to a next stage inhibited output by permitting a third switch element and a sixth switch element to have conductive types to be mutually different and, simultaneously, connecting them in parallel between the output inhibited input and next stage inhibited output. CONSTITUTION:The source of a MOS transistor N3K to connect an inverted signal output OK to a gate and the source of a MOS transistor P3K to connect a connecting terminal QK to the gate are connected to an inverted output inhibited input the inverse of TIK, and the drain of the MOS transistor P3K, the drain of a MOS transistor N1K, the source of a MOS transistor N2K, and the drain of the MOS transistor N3K are connected to an inverted next stage inhibited output the inverse of TOK. In such a way, since the transistor N3K and P-channel MOS transistor P3K have the conductive types to be mutually different and they are connected in parallel between the inverted output inhibited input the inverse of TIK and inverted next stage inhibited output the inverse of TOK, the inverted next stage inhibited output the inverse of TOK is not made into a floating condition.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an associative memory (Content Address
The present invention relates to a prioritized address encoder used to encode a plurality of matching address signals such as ssabjeMemory (CAM) in a certain order and obtain a binary address output.

[Conventional technology]

The basic function of CAM is to input reference data, contrary to normal memory, and output data that matches the reference data or the address of the stored word, or if a match is obtained for multiple words. In some cases, a normal encoder cannot provide the correct encoded output. That is, before applying signals to a normal binary encoder, it is necessary to set an appropriate order and synchronize with a clock signal so that only one signal is at an ON potential and sequentially switched and output.

The functions that the priority address encoder should have will be explained below. Here I = (1,, l,, l+...
・1,. 1. ) is the input signal vector, 0 = (0,1
, 04, l+... Paste, Oo) as the output signal vector, A
=(8., 8□-1,...A+, Ao), (n=2''
′”−]) is the output address, and the priority of the input signal is 1.
．． , >IJ (n≧K>j≧0). On the other hand, C
3 is a signal input from the cell 1, and C2 is a clock signal manually input. This function first captures the input value by the signal applied to the set signal C1, and then outputs the input values in order of priority in synchronization with the clock signal applied to the clock signal C2. That is what it is. Here, the conversion from the input signal vector I to the output signal MKU1HELO is performed according to the rules described below.

(I) When a logic "1" exists or does not exist at one place in the element of the input signal vector I, 0=I (first clock) 0-([1,0,...0.0 ) From the second clock onwards) (II) Logic “
1゛.

or two or more I- locations, for example, IJ, 1. There is a logical ``1'' in three places, and if i>j>k, then 1=(0,..., [1,1,, [1,..., I),
1. [), ..., [], 1. ,0. ..., fl)
(Input signal vector) i j k O=((], ..., 0.I, [1, ..., 0,0.
[],...,0,0,0. ..., 0) (first clock)] 0' = (0, ..., O, fl, [], ..., [),
1. [1,..., [1,0,0,...,0) (second
clock) n = (o, ..., o, o, o, ...,
0, 0, 0. ..., 0. I, (], ..., 0) (3rd clock) Q = = (Q, ..., [1, 0, [+,
..., [), 0. [1,..., [1, [1,0,...
..., 0) (from the 4th clock on) To summarize the above, as an element of the output signal vector O, a logic "1" exists either in one place or does not exist at all, and there are two input value numbers. Even if logic "1" exists in multiple locations as an element of vector I, it is output in order of priority according to the clock signal.

The output signal 1-0 obtained as described above is sent to encoder 1 by the address encoder.

This encoder is a normal one. If it is logical ``l'', it is obtained as the binary code of i or the output address A.

FIG. 3 is a circuit diagram, without showing the second circuit element, of a conventional priority address encoder disclosed in, for example, Japanese Patent Publication No. 1595/1983. In Figure 3, ■
, is a signal input, C1 is a set signal input, C2, C, is a clock signal input, (), is a signal output, A is an ND circuit to N, B is an inverter, S+ is +S2 is +S:+ is +'+ +85 is a switch circuit consisting of an N-channel 08 transistor, and 5611 is a switch circuit consisting of a P-channel MO8+- transistor. Tlk is an inverted output prohibition input, and if "l" is applied as an input signal at one or more locations in an address with a higher priority (in this example, a circuit element with a number greater than k) and is output as an address. °゛0゛ is applied. Te3 is an inverted next stage inhibition output. 82k.

":lk +" 4 is a reset switch circuit, which inputs - "1" to input signal 1 and outputs inverted output inhibition output TI.
When the signal output Ok = ``1'' is outputted as an address, the clock signal C2, C,
Accordingly, the connection terminal Q is reset to 0". Once reset, due to the output holding function of the switch S2h, the reset 1 is set by the switch S1y.
~ Maintain and control the state. Note that the lock signal C3 is the inverse of the clock signal C2, and its state is shown in FIG. In FIG. 4, (a) shows the set signal C1, (b) and (c) show the clock signals C2 and C3,
Moreover, .about.T4 indicates the time width of one cycle of the clock signal C2+03.

The operation of the circuit of FIG. 3 is classified as follows according to the input signal.

(]) Reverse output prohibition Manual power Tlk-'"1" and switch SIk connects connection terminal Q,
and switch S2□+81k+”4
Reset by k 1~ or if not done, NA
Since both inputs to the ND circuit A are l'', the output Ok of the signal 55 is Ok-'l''.

1, on the other hand, switch S5. is ON state, switch S G k
Since it is in the OFF state, the inverted next stage inhibition output TOk is TOk = "O".

(2) When the inverted output inhibition input 'l'l, -' is “1”,
And the connection terminal Q is set to "0'' by the switch SIk, or the switch S2□+8
When the reset by 3k+'''lk has been completed, one of the inputs to the NAND circuit A is "'O°", so the signal output Ok is Ok-°"0".

On the other hand, since the switch 85 is in the OFF state and the switch 86 is in the ON state, the inverted next stage inhibit +1-output "rOk" is TOk="0".

(3) Inversion output inhibit input TIk - "0°'" and switch Slk connects connecting terminal Qb to "l" to cell 1, and switch 82 k + "3 k + S
, lk (1-h) is not performed, one of the inputs to the NAND circuit A is "0", so the signal output Ok is "0".

On the other hand, switches S, , are in the ON state, and switch 5ett is in the ON state.
is in the OFF state, so the inverted next stage inhibition output] ゛0. is TOk="0".

(4) Is the inverted output inhibit input Tlk = “0” and the connection terminal Qk is set to “0'' by the switch Slk, or is +84k set to the switch S2□+83?
When the reset by
k-“0゛.

On the other hand, since the switch 85 is in the OFF state and the switch 86 is in the ON state, the inverted next stage inhibition output TOk is
k = “0”.

Table 1 shows the above relationship as an input/output truth table.

Table 1 Next, a conventional 3-word input encoding circuit shown in FIG. 5 will be explained. Here, as shown in Fig. 3, three turning circuit elements are arranged in one row, and "l"' is input to the inverted output prohibition input I2 of the circuit element row 2 and 1, and then the second circuit element The inversion next stage inhibition output T02 is connected to the inversion output inhibition formula 1 of the 1st circuit element, and the inversion method/stage inhibition output TO3 of the 1st circuit element is connected to the inversion output inhibition input h13 of the 0th circuit element. The inverted next stage inhibit output TOo of the 0th circuit element is opened. Here, I − (1,,,
! ,,1. ) is the input signal vector, 0−(02,0□,
0. , ) is the output signal I~. In the example in FIG. 5, the priorities are l, , > 1. >Io.

Now, assuming I = (+, 1.1), the timing in Figure 4
Table 2 summarizes the operations of the example shown in FIG. 5 according to the chart.

Table 2 (Problems to be Solved by the Invention) As described above, the conventional priority-based address encoder is constructed by cascading as many circuit elements as the number of words shown in FIG. 3. However, in the circuit element shown in FIG. 3, the inversion output inhibiting force Tlk = '0' and the connection terminal Qk is set to '0' by the switch 81k, or the switch S2k + S:lk
If the reset by +S4k has been completed, the P-channel MO3) switch circuit 86 consisting of a run transistor
k is turned on or the source of the P-channel MOS transistor 86 is set to "0", so that the voltage is sufficiently low.
There was a problem in that the next-stage inversion inhibition output TOk, which does not become N and becomes "0", becomes a floating state, and there is a possibility that the signal may not be transmitted accurately.

The present invention was made to solve the above-mentioned problems, and it is an object of the present invention to obtain a stable encoding circuit by avoiding the next stage inhibited output or floating state.

(Means for Solving the Problems) An encoding circuit according to the present invention includes a first encoder circuit controlled by a signal input, one end of which is connected to a first power supply, and the other end of which is connected to a signal output. The first switch element of the conductor type 1L (for example, the transistor Plk in FIG. 1, which will be described later, or the second transistor N4. , the other end of which is connected to the above-mentioned signal output, and the second switch element of the first conductive layer controlled by the output inhibit input (for example, the one-heran transistor P2k in FIG. 1 described later, or the transistor N5k in FIG. 2) ), and a third switch element of the first conductivity type controlled by the signal input (for example, Transistor P3k in FIG. 1 or transistor N6 in FIG. A fourth switch element of the second conductivity type controlled by
) and: a fifth switch element of a second conductivity type controlled by the output prohibition input indicated by l-, whose one end is connected to the next stage prohibition output and the other end is connected to the signal output; For example, a transistor N25 in FIG. 1 (described later) or a transistor P5k in FIG. The second controlled by the output
A sixth switching element f (for example, the transistor Nak in FIG. 1, which will be described later, or the transistor 1 in FIG. 2) 1, □) of the conductivity type.

[Effect]

In this invention, the third switch element and the sixth switch element have different conductivity types, and are connected in parallel between the output prohibition input and the next stage prohibition output, so that information on the output prohibition input is transmitted. Accurately transmit to the next stage inhibition output.

〔Example〕

FIG. 1 is a circuit diagram of the first circuit element in an embodiment of the encoding circuit according to the present invention. In FIG. 1, the same parts and symbols as those in FIG. 3 do not show corresponding parts. Nl
k + N2 k + N3 k is N-channel MOS
l-transistor, Pl k + 1) 2 k + P
:lk is a P-channel MO8+-Lancissistor, MO' with the connection terminal Q connected to K1-; Connect the source of k to the power supply V11, and connect the MOS 1 to the train of the transistor Plk and the lock os transistor I)2. MO with the train and reverse output prohibition human power TIk connected to the gate.
S) Output the inverted signal from the train to the run transistor N2.
MOS connected to k and connecting terminal Q to the gate
The source of the transistor Nlk is grounded, and the inverted signal output is 0.
．． ) - MOS whose gate is connected to the source of the MOS transistor N3 and connection terminal Q, MOS whose source of the MOS transistor P3 is connected to the inverted output inhibit input TIk, and the train of the MOS transistor P3 and the MOS
) The train of the run transistor Nlk and the source of the run transistor 82 and the train of the run transistor N3 are connected to the inverted next stage inhibition output i-1.

The operation of the circuit shown in FIG. 1 is classified as follows according to the input signal.

(1) Reverse output is inhibited by human power "k-"l", and the connection terminal C1k is set to °°1" by the switch S+k, and the reset 1~ is performed again by the switch S2+1+"3k+Lk. If not, N-channel MOS 1 to run transistors N+b and N21 are both in the ON state, so the call output 0□ is O2-“1”.

On the other hand, N-channel MOS) run transistor N: l k
is OFF state, P channel MO8) Runsistor 1) 1
is in the OFF state, N-channel MOS transistor Nl
Since k is in the ON state, the inverted next stage inhibition output TOk is
TOk-"0"'.

(2) Is the inverted output inhibit input Th-“L” and the connection terminal Q is set to “0’” by the switch Slk, or is the switch 82k+”:L
k + "4 When the reset by k is completed, the P channel MO3) run transistor 1) is in the ON state, so the signal output is 0., 0.-"0''.

On the other hand, N-channel MOS) is ON for run transistor N3.
Status, P channel MO8) - Runsistor P3k is ON state, N channel MOS 1 - Runsistor Nlk
is in the OFF state, so the inverted next stage inhibition output TOk is
It is Tok-1゛.

(3) Inversion output prohibition input T1. - "0" and is set to connection terminal Q, or '1' by switch Slk, and switch S2h +S:+ is reset by S, nt or not, P channel MO
3) Since the run transistor P2 is in the 01Lt state, the signal output Ok is Ok=°"0".

On the other hand, N-channel MOS) is ON for run transistor N3.
state, P-channel MOS transistor P3 is OFF
Status, N-channel MOS transistor Nlk is ON
state, the inverted next stage inhibition output TOh is TOk.
-°゛0''.

(4) Inversion output inhibit input TI, = “0” and connection terminal Qk is set to “0” by switch Slk, or switch S2h +33k +84
If the reset by k has been completed, the P channel M
O8) Since both run transistors 'Ill+P2 are in the ON state, the signal output is 0. is o,=“o”.

On the other hand, N-channel MOS) is ON for run transistor N3.
state, P channel MO3) Run transistor P3 is ON state, N channel MOS) - Run transistor Nlk is OF
Since it is in the F state, the inverted next stage inhibition output T (h is TOk
- “o”.

Thus, according to the embodiment of the present invention, N channels M
The O8l-run transistor Nlk and the P channel/V channel MOS transistor P3 have different conductivity types, and are connected in parallel between the inverted output inhibit input TI and the inverted next stage inhibited output TOk. The stage inhibit output TOk never becomes a floating state.

FIG. 2 is a circuit diagram of the second circuit element in another embodiment of the encoding circuit according to the present invention.

In FIG. 2, the same reference numerals as in FIG. 1 indicate corresponding parts. P4, P', Plik is P channel MO3
) Runsistor, N4k, N51L, N6 for N
Channel MOS) - Has a run transistor, connection terminal Q
MOS with k connected to the gate MOS with the source of transistor N4 and output inhibit input TI connected to the gate
l-ground the source of the transistor N,, ik, and connect the MOS
) - 1~rain and MOS to run transistor 84) 1F input Tlk to gate 1 for both train and output to run transistor N5
- MOS 1 connected to the MOS 1 to the 1-rain of the run transistor PThk are connected to the signal output Ok, and the connection terminal Q is connected to the gate of the MOS l-run transistor 1]. Connect the source of 0. to the power supply VB and output the signal 0. MO connected to the Kate
S) A MOS whose gate is connected to the source of the MOS transistor P6 and the connection terminal Q.) A MOS whose source is connected to the output inhibit input TIh, and a train to the MOS transistor N6, a train to the MOS transistor P4, and a MOS transistor connected to the gate of the MOS transistor P6.
OS) The source of the transistor P5t and the train of the MOS transistor P6 are connected to the next stage inhibit output TOk.

In this embodiment, the N-channel MOS transistor N6) and the P-channel MOMOS transistor P6 have different conductivity types, and are connected in parallel between the output inhibit input TI and the next stage inhibit output TOk. Even if the next stage prohibition output TOk is in a floating state, it will not occur.

Note that the operation of this embodiment is similar to that of the embodiment shown in FIG. 1, so a description thereof will be omitted.

(Effects of the Invention) As described above, according to the present invention, it is possible to avoid the next-stage inhibited output or the floating state and accurately transmit the information of the output inhibited input to the next-stage inhibited output. This has the effect of providing a stable encoding circuit.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the second circuit element of an encoding circuit according to an embodiment of the present invention, and FIG. 2 is a circuit diagram showing the second circuit element of an encoding circuit according to another embodiment of the present invention. 3 is a circuit diagram showing the second circuit element of a conventional encoding circuit, FIG. 4 is a diagram showing waveforms of set signal and clock signal input, and FIG. The circuit diagram of the encoding circuit is 1. In the figure, ■ is a signal input, TI is an output inhibit input,
TOk is the next stage inhibition output, Ok is the signal output, P l k
+'2 to +P3k or N411+N5 to +N6 to the first
, the second and third switch elements, Nik, N2, and Ns. or l) □, P, b, Pe, and R are the fourth, fifth, and sixth switch elements. Note that the same reference numerals in the figures indicate the same or equivalent parts. Agent Masu Oiwa A1 [
In Figure 2 Tl

Claims (1)

[Claims] (1) A first device controlled by a signal input, with one end connected to a first power source and the other end connected to a signal output.
a first switch element having a conductivity type of
a second switch element of a first conductivity type controlled by the output prohibition input, the second switch element being connected to the power supply of the device and having one end connected to the output prohibition input; a third switch element of the first conductivity type controlled by the signal input, the other end of which is connected to the next-stage inhibit output; one end of which is connected to the second power source, and the other end of which is a fourth switch element of a second conductivity type that is connected to the next-stage inhibition output and is controlled by the signal input; one end is connected to the next-stage inhibition output and the other end is connected to the signal output; a fifth switch element of a second conductivity type that is controlled by the output prohibition input, one end of which is connected to the output prohibition input, and the other end of which is connected to the next stage prohibition output; , and a sixth switch element of a second conductivity type controlled by the signal output.