JPH0230651U - - Google Patents

Info

Publication number
JPH0230651U
JPH0230651U JP1989096186U JP9618689U JPH0230651U JP H0230651 U JPH0230651 U JP H0230651U JP 1989096186 U JP1989096186 U JP 1989096186U JP 9618689 U JP9618689 U JP 9618689U JP H0230651 U JPH0230651 U JP H0230651U
Authority
JP
Japan
Prior art keywords
circuit
signal
flop
receives
output signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1989096186U
Other languages
Japanese (ja)
Other versions
JPH046280Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1989096186U priority Critical patent/JPH046280Y2/ja
Publication of JPH0230651U publication Critical patent/JPH0230651U/ja
Application granted granted Critical
Publication of JPH046280Y2 publication Critical patent/JPH046280Y2/ja
Expired legal-status Critical Current

Links

Landscapes

  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図a,bは本考案を説明するためのタイミ
ングチヤート、第2図および第3図a〜f、第4
図a〜fはいずれも本考案実施例を示すブロツク
図およびタイミングチヤートである。 1……アンド回路、2……トグル形フリツプフ
ロツプ、3……排他的論理和回路、S〜S
…信号。
FIGS. 1a and 1b are timing charts for explaining the present invention, FIGS. 2 and 3 a to f, and 4.
Figures a to f are block diagrams and timing charts showing embodiments of the present invention. 1...AND circuit, 2...Toggle flip-flop, 3...Exclusive OR circuit, S1 to S6 ...
…signal.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] データクロツク信号とデジタルデータ信号とを
入力とするアンド回路と、このアンド回路の出力
信号を入力とするトグル形フリツプフロツプと、
このトグル形フリツプフロツプの出力信号とPN
コード信号とを入力する排他的論理和回路とから
成ることを特徴とする差動位相偏移変調用論理回
路。
an AND circuit that receives a data clock signal and a digital data signal; a toggle flip-flop that receives an output signal of the AND circuit;
The output signal of this toggle type flip-flop and PN
1. A logic circuit for differential phase shift keying, comprising: a code signal; and an exclusive OR circuit inputting a code signal.
JP1989096186U 1989-08-16 1989-08-16 Expired JPH046280Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1989096186U JPH046280Y2 (en) 1989-08-16 1989-08-16

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1989096186U JPH046280Y2 (en) 1989-08-16 1989-08-16

Publications (2)

Publication Number Publication Date
JPH0230651U true JPH0230651U (en) 1990-02-27
JPH046280Y2 JPH046280Y2 (en) 1992-02-20

Family

ID=31321028

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1989096186U Expired JPH046280Y2 (en) 1989-08-16 1989-08-16

Country Status (1)

Country Link
JP (1) JPH046280Y2 (en)

Also Published As

Publication number Publication date
JPH046280Y2 (en) 1992-02-20

Similar Documents

Publication Publication Date Title
JPS60103557U (en) Mold
JPH0369931U (en)
JPH0485922U (en)
JPS6425770U (en)
JPS61143335U (en)
JPS6170429U (en)
JPH02103926U (en)
JPS6338420U (en)
JPS62158535U (en)
JPS62138379U (en)
JPH044434U (en)
JPH0246440U (en)
JPS63129333U (en)
JPS6181223U (en)
JPS6355628U (en)
JPH01147441U (en)
JPS6095571U (en) watch dial
JPH0246435U (en)
JPS5986742U (en) Programmable timing generation circuit
JPS6183346U (en)
JPS62143345U (en)
JPH0399368U (en)
JPS62161399U (en)
JPH036325U (en)
JPS5828441U (en) Constant generator circuit