JPH046280Y2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Field of Application] The present invention relates to a logic circuit particularly intended for differential phase shift keying.

[Prior Art] The main modulation methods in the field of digital data communication usually involve modulating a PN code signal with digital data of 0 and 1, for example, Japanese Patent Laid-Open No. 55-34578.
As disclosed in the issue, BPSK (Bi−
Phase-Shift-Keying) modulation method or Differential Phase Shift
Keying: DPSK) modulation method, and this DPSK
In recent years, modulation methods have been widely adopted in spread spectrum (SS) communication and the like.

The principle of DPSK modulation in SS communication is that "if the digital data is a logic "1", the phase of the immediately preceding PN code is inverted; if it is a logic "0", the phase of the immediately preceding PN code is continued." PN code is periodic pseudo noise (Pseudo Noise:
PN) code.

FIG. 1 is a waveform chart (timing chart) explaining the operation, in which a shows the digital data signal waveform and b shows the waveform of the DPSK-modulated PN code signal. As is clear from Figure 1b, PN
The phase of the code signal changes in accordance with the logic level of the digital data signal. For example, between t ₂ and t ₃ , the phase just before that corresponds to the logic "0" of the digital data signal, and during t Between ₃ and _t4 , the phase changes so that the previous phase is inverted in response to logic "1". In general, the cord length N is 2 ⁿ
It is possible to set a value of -1 (n=3, 4, 5...) to correspond.

[Problem to be solved by the invention] By the way, the demodulation circuit for the data modulated by BPSK has a complicated configuration, and the above-mentioned
The specific hardware configuration of the DPSK modulation unit in SS communications and the like has not been very clear so far, and it is thought that it has a relatively complicated circuit configuration.

[Means for Solving the Problems] The present invention has been made from the above-mentioned viewpoint, and has a simple circuit configuration in which an AND gate and a toggle flip-flop are provided on the input side of the alistic OR circuit. Its purpose is to configure a DPSK modulation section in the early 2000s, and its characteristics are that it converts a digital data signal into a signal of another pattern using the AND gate and toggle type flip-flop, and then uses that signal to convert the digital data signal into a signal of another pattern. The purpose is to modulate the PN code signal with an alistic OR circuit to perform the desired DPSK modulation.

[Embodiments] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 2 is a block diagram showing a logic circuit for DPSK modulation according to an embodiment of the present invention, in which 1 is an AND circuit which receives data clock signal S ₁ and digital data signal S ₂ as input, and 2 is a toggle type flip-flop that functions as the AND circuit. 1's output signal _S3 is input, and 3 is an alistic OR circuit which connects the toggle type flip-flop 2.
The output signal S ₄ and the PN code signal S ₅ are input.
Outputs the DPSK signal _S6 as an output signal.

FIGS. 3a to 3f are waveform diagrams showing the operation of the above logic circuit, and show the signals S ₁ to S ₆ , respectively.

First, the data clock signal S ₁ as shown in FIG.
And the AND circuit 1 to which the digital data signal _S2 as shown in Fig. 3b is input, outputs the signal as shown in Fig. 3c.
The toggle flip-flop 2 which outputs S ₃ and which subsequently receives this signal S ₃ is activated by, for example, a rising edge of the signal S ₃ , and its function causes the signal S ₃ to change from the bottom level to the high level. The output signal level is inverted each time, and a signal _S4 as shown in FIG. 3d is output. Note that it is also possible to operate by the falling edge of the signal _S3 in the same way as the rising edge.

Furthermore, the alistic OR circuit 3 to which the signal _S4 and the PN code signal _S5 as shown in FIG. 3e are inputted outputs the signal _S6 as shown in FIG. 3f as a DPSK signal.

With such a configuration, the DPSK modulation section can be realized with a simple circuit configuration.

Figures 4a to 4f show other embodiments of the present invention, especially when the PN code signal _S5 is set to have a code length N=7 for one period as shown in Figure 4e. This shows the state of change in the DPSK signal.

According to the principle of DPSK modulation, Figure 3 a-f
As in the case of , the alistic OR circuit 3 is shown in FIG.
A signal _S6 like this is output as a DPSK signal.

[Effects of the invention] As is clear from the above description, the invention provides an AND circuit which receives a data clock signal and a digital data signal as input, a toggle type flip-flop which receives an output signal of this AND circuit, and The DPSK modulation section can be realized with a simple circuit configuration since it is configured to include an alistic OR circuit which inputs the output signal of the toggle type flip-flop and the PN code signal.

Therefore, since the number of component parts can be reduced, costs can be reduced, and at the same time, the occurrence of failures can be suppressed based on the simple configuration, so reliability can be improved.

Therefore, the present invention can be widely applied to various digital communication fields including SS communication.

[Brief explanation of the drawing]

FIGS. 1a and 1b are timing charts for explaining the present invention, FIGS. 2 and 3 a to f, and 4.
Figures a to f are block diagrams and timing charts showing embodiments of the present invention. 1...AND circuit, 2...Toggle type flip-flop, 3...Trusive OR circuit, _S1 to _S6 ...Signal.

Claims (1)

[Scope of utility model registration request] an AND circuit that receives a data clock signal and a digital data signal; a toggle flip-flop that receives an output signal of the AND circuit;
The output signal of this toggle type flip-flop and PN
1. A logic circuit for differential phase shift keying, comprising: a code signal; and an alistic OR circuit input with a code signal.