JPH02307231A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To uniformly form a recess shape and to simultaneously form a T-shaped gate by previously etching a spacer layer necessary to form an upper recess, forming an upper recess region, then providing a new spacer, forming a lower recess region, and extending the width of the opening after the lower recess is formed. CONSTITUTION:A spacer layer 3 and a resist layer 4 are laminated on an active layer 2 formed on a semiconductor substrate 1, an opening 5 is provided at the layer 4, and the spacer 3 is selectively etched. Then, the layer 2 is etched with the layer 3 as a mask to form an upper recess region 6, the layer 4 is then removed, and a second spacer layer 9 and a second resist layer 10 are laminated. Then, an opening 11 is formed at the layer 10, the layer 9 is selectively removed by etching, the layer 2 is etched with the layer 9 as a mask to form a lower recess region 6. Then, the opening 11 is extended by dry etching, a gate electrode metal is deposited on the whole surface, the gate metal on the layer 10 is removed by a lift-off method to form a T-shaped gate electrode 8.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of manufacturing a semiconductor device having a recessed structure.

[Conventional technology]

FIGS. 2(a) to 2(g) are diagrams showing a conventional method for manufacturing a semiconductor device, and are cross-sectional views showing a semiconductor device having a multi-stage recess structure in the order of its manufacturing steps. In these figures, 1 is a substrate made of gallium arsenide or the like, 2 is a semiconductor active layer formed on this substrate 1, and 3 and 4 are spacer layers such as SiN films laminated in sequence on this semiconductor active layer 2. a resist layer; 5 is an opening formed in the resist layer 4; 6 is a recess region formed in the semiconductor active layer 2; 7 is a stepped portion of the recess region 6; 8 is a gate electrode; ' is the gate electrode metal.

Next, a method for manufacturing a semiconductor device having a multi-stage recess structure will be explained with reference to FIGS. 2(a) to 2(g).

First, as shown in FIG. 2(a), a spacer layer 3 is placed on a semiconductor active layer 2 formed on a substrate 1. A resist layer 4 is laminated, and an opening 5 is formed by photolithography. Next, in FIG. 2(b), the spacer layer 3 is selectively etched away by dry etching such as RIE. Next, as shown in FIG. 2(C), a recess region 6 is formed in the semiconductor active layer 2, and then, in FIG. 2(d), only the spacer layer 3 is selectively side etched. Next, in FIG. 2(e), the side-etched spacer layer 3 is
The semiconductor active layer 2 is etched using the mask as a multi-stage (
In this embodiment, the recess region 6 is enlarged (in two steps) and the step portion 7 is formed. Note that the upper side of the stepped portion 7 is referred to as an upper recess area, and the lower side is referred to as a lower recess area. Next, Figure 2 (
In f), a gate electrode metal 8' is laminated over the entire surface by vapor deposition or the like. Next, the resist layer 4 is formed by a lift-off method.
The upper gate electrode metal 8' is removed, and a gate electrode 8 is formed within the recess region 6. Although not shown, source and drain electrodes are formed, and together with the gate electrode 8, form a transistor.

(Problems to be Solved by the Invention) A conventional semiconductor device having a multi-stage recess structure is formed as described above, but when side etching the spacer layer 3, wet etching is used, so it is difficult to control the amount of etching. Therefore, there was a problem that the recess shape formed in the subsequent process could not be made uniform.

The present invention was made to solve the above-mentioned problems, and provides a semiconductor device in which a recess shape can be formed uniformly and a T-shaped gate can be formed at the same time.

The purpose is to obtain a manufacturing method.

(Means for Solving the Problems) In the method for manufacturing a semiconductor device according to the present invention, in order to eliminate the site etching step, the spacer layer necessary for forming the upper recess is first etched, and after forming the upper recess region, This method includes a step of providing a new spacer layer, forming a lower recess region, and widening the width of the opening after forming the lower recess.

In the method for manufacturing a semiconductor device of the present invention, the spacer layer necessary for forming the upper recess is etched first, so there is no side etching step, and the amount of etching is controlled by the width of the opening. Therefore, it becomes possible to form a uniform recess shape, which also leads to uniformity of device performance.

Further, by providing a step of widening the opening after forming the recessed region, the shape of the gate electrode maintains a narrow length in the portion in contact with the semiconductor active layer, and becomes larger in the upper portion. Since this is a so-called T-shaped gate electrode, the gate resistance can be lowered while keeping the gate length small.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG.

1(a) to 1(h) are cross-sectional views showing the manufacturing process of a semiconductor device having a multi-stage recess structure showing an embodiment of the present invention, and in the figures, 1 to 8 are the same as those in FIG. 2. However, here, 3 is referred to as a first spacer layer, 4 is referred to as a first resist layer, and 5 is referred to as a first opening. 9 is a second spacer layer laminated after removing the first resist layer 4; 10;
is a second resist layer laminated on this second spacer layer 9, and 11 is a second opening formed in this second resist layer 10.

First, in FIG. 1(a), a first opening 5 is formed in the first resist layer 4. As shown in FIG. At this time, the width of the first opening 5 is set to a width necessary to form the upper recess region. Therefore, there is no need to side-etch the first spacer layer 3 as in the conventional example, leading to uniformity of the recess shape.

Next, as shown in FIG. 1(b), the first spacer layer 3 exposed by the formation of the first opening 5 is selectively etched away. Next, in FIG. 1C, the semiconductor active layer 2 is etched using the first spacer layer 3 of FIG. 1 as a mask to form an upper recess region.
The resist layer 4 is removed. Next, in FIG. 1(d), after forming a second spacer layer 9, a second resist layer 1o is laminated as shown in FIG. 1(e). after that,
The second opening 11 is formed by photolithography, and the second spacer layer 9 is selectively etched. At this time, the second opening 11 has a width corresponding to the gate length (Lg),
It is formed to fit within the upper recess region so that multi-stage recess formation can be performed. In FIG. 1(e), using the second spacer layer 9 as a mask, the semiconductor active layer 2 is etched to form a step portion 7 and to complete the multi-step recess region 6. After this, as shown in FIG. 1(f), the second
The resist N10 is etched to widen the second opening 11. Etching at this time is RIE or RI.
Good dry etching such as BE. Next, as shown in FIG. 1(g), a gate electrode metal 8' is deposited over the entire surface, and unnecessary gate electrode metal 8' on the second resist layer 10 is removed by a lift-off method. As shown in (h), the gate electrode 8 is completed.

This gate electrode 8 has a cross-sectional shape with a narrow gate length (
Lg), and the upper part is large, resulting in a so-called T-type gate structure, which can reduce gate resistance.

〔Effect of the invention〕

As explained above, the present invention forms a multi-stage recess region by separately providing the spacer layers used for forming the upper recess region and the lower recess region, thereby eliminating the side etching process of the spacer layer, which is difficult to control. This improves the controllability of forming each recess region and makes the recess shape uniform.

In addition, by widening the opening after forming the recessed area,
This has the effect of easily obtaining a T-type gate structure and reducing gate resistance.

[Brief explanation of the drawing]

FIG. 1 is a process sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a process sectional view showing a conventional method for manufacturing a semiconductor device. In the figure, 1 is a semiconductor substrate, 2 is a semiconductor active layer, 3 is a first spacer layer, 4 is a first resist layer, 5 is a first opening, 6 is a multi-stage recess region, 7 is a stepped portion, and 8 is a gate electrode, 9 is a second spacer layer, 10 is a second resist layer,
11 is a second opening. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa (2 others) Figure 1, Figure 1, Figure 1, Figure 2 ]ko 11 Second opening procedure amendment (voluntary)

Claims (1)

[Claims] a step of sequentially laminating a first spacer layer and a first resist on a semiconductor active layer formed on a semiconductor substrate, and providing a first opening in the first spacer layer; a step of selectively etching away the first resist layer using the first resist layer as a mask; a step of etching the semiconductor active layer using the first spacer layer opened as a mask to form an upper recess region; removing the resist layer and laminating a second spacer layer and a second resist layer, providing a second opening in the second resist layer, and using the second resist layer as a mask to stack the second spacer layer and the second resist layer; a step of selectively etching away a second spacer layer; a step of etching the semiconductor active layer using the opened second spacer layer as a mask to form a lower recess region;
A T-shaped gate electrode is formed by widening the opening by dry etching, depositing gate electrode metal on the entire surface, and removing unnecessary gate electrode metal on the second resist layer by lift-off method. 1. A method for manufacturing a semiconductor device, comprising the steps of: