JPH02307293A - Mounting of semiconductor device - Google Patents
Mounting of semiconductor deviceInfo
- Publication number
- JPH02307293A JPH02307293A JP12930689A JP12930689A JPH02307293A JP H02307293 A JPH02307293 A JP H02307293A JP 12930689 A JP12930689 A JP 12930689A JP 12930689 A JP12930689 A JP 12930689A JP H02307293 A JPH02307293 A JP H02307293A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- sheet
- solder paste
- mounting
- solder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/12—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns
- H05K3/1216—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns by screen printing or stencil printing
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、半導体装置をプリント基板上に表面実装す
る半導体装置の実装方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for mounting a semiconductor device on the surface of a printed circuit board.
第４図は従来の半導体装置のプリント配線基板（以下Ｐ
ＯＢと呼ぶ）上へ表面実装するプロセスのフローチャー
トを示し、第５図ａ ”’−’ ｅは上記フローチャー
トに対応した各工程を示す斜視図及び側面図である。図
において、ｌはＰＯＢ、２はこのＰＯＢｋ、の配線パタ
ーン、２ａは半導体装置４を実装する部分の配線パター
ン、３は半田ペースト５を印刷するためのスキージ（ゴ
ム製のへら）、６はメタルマスク、５ａは印刷され２千
田ペーストである。Figure 4 shows the printed wiring board (hereinafter referred to as P) of a conventional semiconductor device.
Fig. 5a''-'e are perspective views and side views showing each process corresponding to the above flowchart. In the figure, l is POB, 2 is the wiring pattern of this POBk, 2a is the wiring pattern of the part where the semiconductor device 4 is mounted, 3 is a squeegee (rubber spatula) for printing the solder paste 5, 6 is a metal mask, 5a is the printed 2nd line It is a paste.
次に動作について説明する。ＰＯＢ ｌ上に半導体装置
４及びチップ部品（図示せず）３牛田付けする技術にお
いて、特に表面実装型部品を実装する場合、第４図に示
すフローチャートに従って行う０
まず、ＰＯＢ ｌ上の半田付けを行う部分、即ち、半導
体装置の実装を行う配線パターン２ａ部分に、半田と７
ラツクス等からなる半田ペースト５を印刷する。この印
刷しこ当って半田の必要部分のみに開口Ｂ６ａをあけた
メタルマスク６上に半田ペースト５を供給し、スキージ
３を矢印の方向へ移動させて、半田ペースト５をＰＯＢ
Ｉ上の半田を必要とする配線パターン２ａ上に印刷する
（第５図す、ｃｚｄ参照）。次に、パターン詔緑等によ
り搭載すべき半導体装置４及びチップ部品（図示せす）
を配線パターン２上に位置合わせし、搭載する。しかる
慢、赤外線ＤＯ熱等の加熱炉内にて半田ペースト５ａを
溶隔し、洗浄工程において余分なフランクス分を除去す
ることにより、実装を完了していた（第５図θ珍照）。Next, the operation will be explained. In the technique of soldering the semiconductor device 4 and chip components (not shown) 3 onto the POB l, especially when mounting surface mount type parts, the soldering on the POB l is carried out according to the flowchart shown in Fig. 4. Solder and 7
A solder paste 5 made of lux or the like is printed. After this printing, the solder paste 5 is supplied onto the metal mask 6 which has openings B6a made only in the necessary parts of the solder, and the squeegee 3 is moved in the direction of the arrow to apply the solder paste 5 to the POB.
Print on the wiring pattern 2a that requires solder on I (see Figure 5, czd). Next, the semiconductor device 4 and chip parts (as shown) to be mounted according to the pattern etc.
Align it on wiring pattern 2 and mount it. However, the solder paste 5a was melted in a heating furnace using infrared DO heat, etc., and the excess flanks were removed in a cleaning process, thereby completing the mounting (see θ in FIG. 5).
第６図において、半導体装置４のリードピッチｐは、従
来０．８ｆｌ及び０．６５ｆｆｌ１１と、実装密度の向
上に伴い縮少化される傾向にあり、現任ではＱ、 ５
ｍｍ、将来的には０．４絹ピツチとなることが予想され
る。In FIG. 6, the lead pitch p of the semiconductor device 4 is conventionally 0.8fl and 0.65ffl11, which tends to be reduced as the packaging density improves, and currently Q, 5
mm, and it is expected that it will become 0.4 silk pitch in the future.
このピッチの縮少化に伴い、ＰＯＢＩ上のｃｔ Ｍ パ
ターン２ａの間隔Ｓも狭くなり、ｐ＝ ０．５ ｕ＋で
８＝０２朋、ｐ ＝ ０．４朋でｓ＝ｏ、１５絹となり
、従来の半田ペースト印刷法によると、印刷精度の同上
と印刷する半田ペースト厚のコントロールが大ＫＭ要に
なる。例えば、Ｉ） ＝ ０．４ ｙｍの時に精度良〈
印刷するためには、メタルマスク６の厚みを薄く、Ｑ、
ｌ ｆｆ１ｌｌ＋以下として、配線パターン間へはみ
出しをなくさなけれｉ、１′ならない。しかし、メタル
マスク厚を薄くＴることにより、配線パターン２ａへの
半田供給量が減少するため、第７図に示すような信頼性
上必要な適正な半田のメニスカス５ｂが形成田来ないば
かりか、半田付は不良により、半導体装置４と配線パタ
ーン２ａが接続されないオープン不良が発生するという
問題があった。Along with this reduction in pitch, the interval S between the ct M patterns 2a on POBI also becomes narrower, and when p = 0.5 u+, 8 = 02 ho, when p = 0.4 ho, s = o, and 15 silk, According to the conventional solder paste printing method, the major KM requirements are printing accuracy and control of the thickness of the solder paste to be printed. For example, good accuracy when I) = 0.4 ym
In order to print, reduce the thickness of the metal mask 6, Q,
l ff1ll+ or less, and no protrusion between wiring patterns must be avoided.i, 1'. However, by reducing the thickness of the metal mask, the amount of solder supplied to the wiring pattern 2a decreases, which not only prevents the formation of the proper solder meniscus 5b required for reliability as shown in FIG. However, due to defective soldering, there is a problem in that an open defect occurs in which the semiconductor device 4 and the wiring pattern 2a are not connected.
この発明は上記のような問題点を解消下るためになされ
たもので、適正な半田量を精度よく供玲することにより
、信頼性の高い半導体装置の実装が可能な方法を提供し
ようとするものである。This invention was made to solve the above-mentioned problems, and aims to provide a method that enables highly reliable mounting of semiconductor devices by accurately applying an appropriate amount of solder. It is.
この発明に係る半導体装置の実装方法の半田ペースト供
鮒法は、半田ペースト印刷前Ｇこ千田供ｆｆ８部が開口
されたシートを接着し、その上からメタルマスクを用い
て印刷し、そσＪ後、シー）Ｆ剥離するようにしたもの
である。The solder paste supply method of the semiconductor device mounting method according to the present invention is to glue a sheet with openings in G, Senda, and FF8 parts before printing the solder paste, print on it using a metal mask, and then after σJ. , C) F is designed to be peeled off.
この発明Ｑこおける半田ペースト供帽法は・シートを予
め接着しておくことにより、メタルマスク厚を薄くして
も、適正Ｍの半田ペーストを供給出来、かつシートを剥
離することにより、配ｍパターン間にはみ出した半田ペ
ーストを除天できるため、精度良く印刷出来る。The method for supplying solder paste in this invention is: By adhering the sheets in advance, even if the metal mask thickness is made thinner, it is possible to supply solder paste with an appropriate M, and by peeling off the sheet, it is possible to Since solder paste protruding between patterns can be removed, printing can be performed with high precision.
以下この発明の一実施例を図について説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第１図はこの発明におけるフローチャートを示し、第２
図は上記フローチャートに対応しに各工程を示す側面図
であり、第３図は本発明において使用されるシートの全
体斜視図である。FIG. 1 shows a flowchart in this invention, and the second
The figures are side views showing each step corresponding to the above flowchart, and FIG. 3 is an overall perspective view of the sheet used in the present invention.
図において、ｌはＰＣＩＢ、２はこのＰＯＢＩ上の配線
パターン・２ａは半導体装は４を実装する部分の配線パ
ターン、３は半田ペースト５を印刷するためのスキージ
、６はメタルマスク、６ａＧ；！その開口部、５ａは印
刷された半田ペースト、７（ゴ開ロ部７ａを有するシー
トである。なお、その他者部分は従来例と同じである。In the figure, l is the PCIB, 2 is the wiring pattern on this POBI, 2a is the wiring pattern of the part where the semiconductor device 4 is mounted, 3 is the squeegee for printing the solder paste 5, 6 is the metal mask, 6aG;! The opening 5a is a sheet having a printed solder paste 7 (a corner opening 7a).The other parts are the same as in the conventional example.
次に動作について説明する。基本的にＱコ従来例と同じ
であるため、特に異なる点につき重点吋に説明する。ま
ず、半Ｉｆ１号供給すべきＦｏａｌ上のパターン２ａと
同位１αに、第８図のような開ロアａを有するシート７
を、開ロアａがＰＯＢ ｌ上のパターン２ａと合致する
ように重ねて接着する。このシート７の作成法としては
、−例として感ｙｅ性樹脂を用いて写真製版とエツチン
グ等により上２−の高寸法精度で、ｐｃｎＩ上のパター
ン２ａと同一４７）パターンの開口部７！Ｌをもつ厚み
Ｑ、 ｌ ＭＲ以下に成形する。このシート裏面に接着
剤を塗布し、Ｆｏａｌに接着する。なお、この接着剤の
強度としては、メタルマスクで印刷する際Ｇこずれない
程度であれば良い（第２図ａ、ｂ＃照）。Next, the operation will be explained. Since the Q-co is basically the same as the conventional example, the different points will be explained with particular emphasis. First, a sheet 7 having an open lower a as shown in FIG.
are overlapped and glued so that the open lower a matches the pattern 2a on the POB l. The sheet 7 is made by photolithography and etching using, for example, a ye-sensitive resin, with high dimensional accuracy as shown in the above 2-, and the opening 7 of the pattern 47) which is the same as the pattern 2a on PCNI! Molded to a thickness Q with L, l MR or less. Apply adhesive to the back of this sheet and adhere to Foal. Note that the strength of this adhesive is sufficient as long as it does not cause G to be distorted when printing with a metal mask (see Figures 2a and 2b).
以上のように、シート７を接着後、半田ペースト５をメ
タルマスク６、スキージ３を用いて印刷する。この際、
メタルマスク厚＋！ ０．１ Ｍ肩以下でも艮い。印刷
された半田ペースト５ａの厚みは、メタルマスク厚と上
記シート７の厚みの相となる（第２図Ｑ、ｄ参照）。As described above, after bonding the sheets 7, the solder paste 5 is printed using the metal mask 6 and the squeegee 3. On this occasion,
Metal mask thickness +! Even if it is below 0.1 M shoulder, it will not work. The thickness of the printed solder paste 5a is equal to the thickness of the metal mask and the thickness of the sheet 7 (see Q and d in FIG. 2).
次に、上記シート７をＰＯＢ ｌ上より剥離すると、Ｐ
ＯＢ上の配線パターン２ａがらはみ出てシードア上にに
じんだ半田ペーストをシート７ごと除去することが出来
、配線パターン２ａ通りに半田を供給することが可能と
なる（第２図ｅ参照）。以降の工程は従来例通りである
（第２図ｆ参照）。Next, when the sheet 7 is peeled off from above POB l, P
The solder paste that has protruded from the wiring pattern 2a on the OB and oozed onto the seed door can be removed together with the sheet 7, making it possible to supply solder in accordance with the wiring pattern 2a (see FIG. 2e). The subsequent steps are the same as in the conventional example (see FIG. 2 f).
なお上記シートは、ＰＣＢ ｌ全体に使用しても良いし
、あるいはリードピッチの狭い搭載部品の場所に限定し
て使用しても良い。Note that the above-mentioned sheet may be used for the entire PCB 1, or may be used only for the location of mounted components with a narrow lead pitch.
以上のようにこの発明によれば、半田ペースト印刷前に
シートをＰＣＢ上に重ねてから印刷するため、メタルマ
スク厚が薄くても適正な半田量を得ることが出来、かつ
配線パターンよりはみ出し二半田は・シート除去時に同
時に除夫可能なため、容易に精度の良い印刷が可能とな
る。As described above, according to the present invention, since the sheet is stacked on the PCB before printing the solder paste, it is possible to obtain an appropriate amount of solder even if the metal mask is thin, and it is possible to obtain two sheets that protrude from the wiring pattern. The solder can be removed at the same time as the sheet is removed, making it easy to print with high precision.
第１図（Ｊこの発明による実装手順を示すフローチャー
ト、第２図はそのフローチャートに対応する部分工程を
示す側面図、第８図はシートの全体斜視図、第４図は従
来の実装方法における実装手加を示すフローチャート、
第５図はそのフローチャートに対応する工程を説明する
側面図、第６図は従来の方法の問題点を説明するための
半導体装置の斜視図、第７図は第６図の一部分号拡大し
た側面図である。
図中、１はプリント配線板、２．２ａは配線パターン、
４は半導体装置、５．５ａは半田ペースト、７はシート
、７ａはシート開口部である。FIG. 1 is a flowchart showing the mounting procedure according to the present invention, FIG. 2 is a side view showing partial steps corresponding to the flowchart, FIG. 8 is an overall perspective view of the sheet, and FIG. 4 is a mounting method according to the conventional mounting method. A flowchart showing the steps,
FIG. 5 is a side view illustrating the process corresponding to the flowchart, FIG. 6 is a perspective view of a semiconductor device to explain the problems of the conventional method, and FIG. 7 is a side view showing an enlarged part of FIG. It is a diagram. In the figure, 1 is a printed wiring board, 2.2a is a wiring pattern,
4 is a semiconductor device, 5.5a is a solder paste, 7 is a sheet, and 7a is a sheet opening.
Claims (1)
プリント配線板上の配線パターン上に半田付けするため
の半田を供給する方法として、半田供給部に開口部を設
けたシートをプリント配線板に接着し、半田ペーストを
上記開口部中へ供給して後、上記シートを上記プリント
配線板より剥離し、さらにその後、半導体装置を実装す
るようにしたことを特徴とする半導体装置の実装方法。When mounting a semiconductor device on a printed wiring board, a sheet with an opening in the solder supply section is bonded to the printed wiring board as a method of supplying solder for soldering onto the wiring pattern on the printed wiring board. . A method for mounting a semiconductor device, characterized in that after supplying solder paste into the opening, the sheet is peeled off from the printed wiring board, and then the semiconductor device is mounted.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12930689A JPH02307293A (en) | 1989-05-23 | 1989-05-23 | Mounting of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12930689A JPH02307293A (en) | 1989-05-23 | 1989-05-23 | Mounting of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02307293A true JPH02307293A (en) | 1990-12-20 |
Family
ID=15006303
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12930689A Pending JPH02307293A (en) | 1989-05-23 | 1989-05-23 | Mounting of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02307293A (en) |
-
1989
- 1989-05-23 JP JP12930689A patent/JPH02307293A/en active Pending
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