JPH0342894A - Packaging of semiconductor device - Google Patents

Packaging of semiconductor device

Info

Publication number
JPH0342894A
JPH0342894A JP1178418A JP17841889A JPH0342894A JP H0342894 A JPH0342894 A JP H0342894A JP 1178418 A JP1178418 A JP 1178418A JP 17841889 A JP17841889 A JP 17841889A JP H0342894 A JPH0342894 A JP H0342894A
Authority
JP
Japan
Prior art keywords
solder
sheet
solder paste
semiconductor device
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1178418A
Other languages
Japanese (ja)
Inventor
Yasuki Ikeda
池田 泰規
Haruo Shimamoto
晴夫 島本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP1178418A priority Critical patent/JPH0342894A/en
Publication of JPH0342894A publication Critical patent/JPH0342894A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3465Application of solder

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

PURPOSE:To supply the proper amount of solder with high accuracy by putting a solder paste that is applied in advance to a film on top of a printed wiring board (POB) and then, performing the transfer of a pattern. CONSTITUTION:A resist 9 consisting of a photosensitive resin is stuck to a film 8 consisting of a material which has poor fitting to a flux in a solder paste. Then, a pattern fitting into each land 2a on a POB 1 to which solder is to be supplied is exposed and developed on the resist 9 by photolithography and then, an opening 9a is formed at a part to be applied with the solder paste 5a. Subsequently, using the opening 9a as a mask, the solder paste 5a is applied on the opening 9a and then, the solder paste 5a is supplied only into the opening 9a. After that, the resist 9 is peeled off physically from the film 8 and a solder sheet 7 is prepared. The solder sheet 7 is bonded onto each land 2a after putting its sheet on top of each land so that its sheet is fit to the land. Subsequently, the film 8 of the solder sheet 7 is peeled off and each semiconductor device 4 is soldered to the solder paste 5a.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、半導体装置をプリント基板上に表面実装方
法、特に半田供給部に関するものであるO 〔従来の技術〕 第6図は従来の半導体装置のプリント配線板(以下PO
Bと呼ぶ)上へ表面実装するプロセスの70−チャート
を示す。第7図イ〜ホは上記フローチャートに対応した
各工程を示す斜視図及び側面図である。図において、l
はFOB、2はFOB上の配線パターン、2aは半導体
装fit4を実装する配線パターンで、ランドと呼ばれ
る部分、3は半田ペース) 5aを印刷するためのスキ
ージ、6はメタルマスク、5mは印刷された半田ペース
トである。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for surface mounting a semiconductor device on a printed circuit board, and in particular to a solder supply unit. [Prior Art] Fig. 6 shows a conventional semiconductor device. Equipment printed wiring board (hereinafter referred to as PO
FIG. 70 shows a 70-chart of the surface mounting process (referred to as B). FIGS. 7A to 7E are a perspective view and a side view showing each process corresponding to the above flowchart. In the figure, l
is the FOB, 2 is the wiring pattern on the FOB, 2a is the wiring pattern for mounting the semiconductor device FIT4, the part called land, 3 is the solder paste) 5a is the squeegee for printing, 6 is the metal mask, 5m is the printed It is a solder paste.

次に従来技術について説明する。POB l上に、半導
体装i14及びチップ部品(図示せず)を、半田付けす
る技術において、特に表面実装型部品を実装する場合、
第6図に示すフローチャートに従って行う。第7図に示
すように、ます、POBI上の半田付けを行うランド2
al1分に、半田と7ラツクス等からなる半田ペースト
5を印刷する。この印刷にあたって、半田の必要部分の
みに開口部6aを開けたメタルマスク6上に、半田ペー
スト5を供給し、ゴム状のヘラであるスキージ3を矢印
の方向へ移動させて、半田ペースト5をPOBI上の半
田を必要とする配線パターン認識上に印刷する。次にパ
ターン認識等により搭載すべき半導体装@4及びチップ
部品(図示せず)を配線パターン2上に位置合わせし、
搭載する。しかるのち、赤外*m+熱等の加熱炉内にて
半田ペース) 5aを浴融し、洗浄工程において余分な
フムツクス分を除去することにより実装を完了していた
Next, the conventional technology will be explained. In the technique of soldering the semiconductor device i14 and chip components (not shown) onto the POB l, especially when mounting surface mount type components,
This is carried out according to the flowchart shown in FIG. As shown in Fig. 7, land 2 is soldered on POBI.
In the al1 minute, solder paste 5 consisting of solder, 7 lux, etc. is printed. For this printing, solder paste 5 is supplied onto a metal mask 6 with openings 6a made only in the areas where solder is needed, and the squeegee 3, which is a rubber-like spatula, is moved in the direction of the arrow to spread the solder paste 5. Print on wiring pattern recognition that requires soldering on POBI. Next, the semiconductor device @ 4 and chip components (not shown) to be mounted are aligned on the wiring pattern 2 by pattern recognition, etc.
Mount. After that, the solder paste (5a) was melted in a heating furnace using infrared*m+heat, etc., and the excess adhesive was removed in a cleaning process to complete the mounting.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

第8図において、半導体装置4のリードピッチPは、従
来0.8u及び0.66 flと実装密度の向上に伴い
縮少化される傾向にある。
In FIG. 8, the lead pitch P of the semiconductor device 4 is conventionally 0.8 u and 0.66 fl, which tends to be reduced as the packaging density improves.

従来の半田ペースト印刷法によると印刷精度の向上と印
刷する半田ペースト厚のコントロールが大変重要になる
。例えは、P=0.4ffの時に精度良く印刷するため
には、メタルマスク6の厚みを薄く、例えば0.1 f
l以下として、配線パターン間へのはみ出しをなくさな
ければならない。しかし、メタルマスク厚を薄くするこ
とにより、配線パターン2aへの半田供給重が減少する
ため、第9図に示すような信頼性上必要な適正な半田の
メニスカス5bが形成出来ないはかりか、半田付は不良
により、半導体装置4と配線パターン2aが接続されな
いオーブン不良が発生する問題があった。
With conventional solder paste printing methods, it is very important to improve printing accuracy and control the thickness of printed solder paste. For example, in order to print with high precision when P=0.4ff, the thickness of the metal mask 6 should be made thin, for example, 0.1 f.
The protrusion between wiring patterns must be eliminated by setting the width to less than l. However, by reducing the thickness of the metal mask, the weight of solder supplied to the wiring pattern 2a is reduced, so it is difficult to use a scale that cannot form an appropriate meniscus 5b of solder necessary for reliability as shown in FIG. There is a problem in that due to a defective attachment, an oven failure occurs in which the semiconductor device 4 and the wiring pattern 2a are not connected.

本発明は上記のような問題点を解消するためになされた
もので、適正な半田量を精度よく供給出来る半導体装置
の実装方法を提供することを目的とする。
The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a method for mounting a semiconductor device that can accurately supply an appropriate amount of solder.

〔課題を解決するための手段〕[Means to solve the problem]

この発明に係る半導体装置の実装方法では・POBのラ
ンド邪に相当する部分の鏡像の部分に、予め半田ペース
トを冷布したシートを用い、この予め半田ペーストを#
r布した上記シートをPOBに接Hし、POB上に転写
し、その後シートを剥離し、そしてこの半田ペースト部
分に半導体装置を半田付けにより実装するものである。
In the method for mounting a semiconductor device according to the present invention, a sheet is used in which a cold cloth is applied with solder paste in advance on a mirror image of the area corresponding to the land of the POB, and this solder paste is applied in advance to #
The above-mentioned sheet coated with R cloth is brought into contact with a POB, transferred onto the POB, the sheet is then peeled off, and a semiconductor device is mounted on the solder paste portion by soldering.

〔作用〕[Effect]

この発明における半田シートは、予め塗布する半田ペー
ストの厚みを調整しておくことによって、任意の半田ペ
ースト鍵を供1#+出来、がっシートをH’lllする
ことにより、配線パターン間にはみ出したすせず、半田
ペーストを精度よく塗布出来るため、信頼性の高い半導
体装置の実装を可能にする。
By adjusting the thickness of the solder paste applied in advance, the solder sheet in this invention can be used with any solder paste key. Since the solder paste can be applied with high precision without any interference, it is possible to mount highly reliable semiconductor devices.

〔実施例〕〔Example〕

以下、この発明の一実施例を図について説明する。第1
図に各工程をフローチャートで示す。第2図は上記フロ
ーチャートに対応した各工程を示す側面図である。第8
図は半田シート7の斜視図である。図において、lはP
OB、2aは半導体装置4を実装する配線パターン、5
aは転写された半田ペースト、7は半田シート、8は半
田シート7のフィルムである。その他各部分は従来例と
同じであるため、同一符号を付し、説明は省略する。
An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure shows each process in a flowchart. FIG. 2 is a side view showing each step corresponding to the above flowchart. 8th
The figure is a perspective view of the solder sheet 7. In the figure, l is P
OB, 2a is a wiring pattern for mounting the semiconductor device 4, 5
Reference character a is the transferred solder paste, 7 is a solder sheet, and 8 is a film of the solder sheet 7. Since each other part is the same as that of the conventional example, the same reference numerals are given and the explanation is omitted.

半田を供給すべきPOBI上のパターン2aと同位置、
同パターンに予め半田ペース) 5aを塗布した半田シ
ート7を、POBI上のランド2aと一致するように重
ねて接着する(第2図口)0その後半田シート7のフィ
ルム8を剥がす(第2図へ)。
Same position as pattern 2a on POBI where solder should be supplied,
Solder sheet 7 coated with solder paste (5a) on the same pattern in advance is overlapped and adhered so as to match the land 2a on POBI (Figure 2 opening) 0 Then peel off the film 8 of solder sheet 7 (Figure 2) fart).

この半田ペース) 6aに半導体装Wt4を半田付けす
るO 上記半田シート7の作成法としては、第4図に一例を示
す。先ず、第4図のように半田ペースト中のフラソクス
とはなじみの悪い材料から成るフィルム8(第4図イ)
上に感光性樹脂から成るレジスト9を貼り合せる(第4
図口)。この時のレジスト9の膜厚は、半田付けに必要
な半田量に応じた膜厚に設定する。次に、半田を供給す
べきPOBI上のランド2aと合うパターンを写真製版
により、レジスト9上に露光、現像し、半田ペースト5
aを塗布すべき部分に開口部9aを形成する(第4図へ
)0この開口部9&をマスクとして、その上から半田ペ
ース) 5aを塗布し、開口部9a内にのみ半田ペース
) 5mを供給する(第4図二)。しがるのちに、フィ
ルム8からレジスト9を物理的に剥ML、、半田シート
7を作成する(第4図ホ)、作成した半田シート7を用
いて、第1図のフローチャートに従って、加圧又は加熱
(半田の−m融しない温度)等によって、POBI上の
ランド2aに転写を行い、半田ペース) 5aとはなじ
みの悪い材料から戊るフィルム8を剥がし、半田ペース
) 5aのみをランド5a上に残す。
The semiconductor device Wt4 is soldered to this solder paste) 6a. An example of the method for producing the solder sheet 7 is shown in FIG. First, as shown in Fig. 4, a film 8 (Fig. 4 A) made of a material that is not compatible with the flasox in the solder paste is prepared.
A resist 9 made of photosensitive resin is pasted on top (fourth
Figure mouth). The film thickness of the resist 9 at this time is set to a film thickness corresponding to the amount of solder required for soldering. Next, a pattern that matches the land 2a on the POBI to which solder is to be supplied is exposed and developed on the resist 9 by photolithography, and the solder paste 5 is
Form an opening 9a in the area where a is to be applied (see Figure 4) Using this opening 9& as a mask, apply solder paste (5a) over it, and apply solder paste (5m) only inside the opening 9a. supply (Figure 4 2). After that, the resist 9 is physically peeled off from the film 8, and the solder sheet 7 is created (FIG. 4 E). Using the created solder sheet 7, pressure is applied according to the flowchart in FIG. Alternatively, transfer to the land 2a on the POBI by heating (temperature at which the solder does not melt), etc., peel off the film 8 from the material that is not compatible with the solder paste 5a, and apply only the solder paste 5a to the land 5a. leave on top.

ここでは、半田ペーストをシート塗布した半田シートに
ついて説明したが、第5図は他への実施例として、溶融
した半田をフィルム上に形成した半田シートによるPO
Bl上のランド2aへの半田供給法について説明する。
Here, we have described a solder sheet coated with solder paste, but Fig. 5 shows another example of PO using a solder sheet in which molten solder is formed on a film.
A method of supplying solder to the land 2a on Bl will be explained.

フィルム8上に導電性があり、半田とは合金を作らない
薄膜10の金属を成膜する(第5図口)。
A thin metal film 10 that is conductive and does not form an alloy with solder is formed on the film 8 (see Figure 5).

この上にレジストリを塗布しく第5図ハ)・写真製版よ
り開口9.9aを設け(第5図二)、下地金属lOをメ
ツキの電極として、半田を開0部に形成する(第5図ホ
)。
Apply a resist on top of this (Fig. 5 c) and create an opening 9.9a by photolithography (Fig. 5 2), and use the base metal 1O as a plating electrode to form solder in the opening 0 (Fig. 5). e).

しかるのち、半田5aを熱源により溶融し固化後、レジ
スト9を除宏する(第5図へ)。かくして、得た半田シ
ート7により、第1図、第2図の手順でランド2a上に
半田層5aを形成し、半導体装置を装着する。
Thereafter, the solder 5a is melted and solidified by a heat source, and then the resist 9 is removed (see FIG. 5). Using the thus obtained solder sheet 7, a solder layer 5a is formed on the land 2a by the steps shown in FIGS. 1 and 2, and a semiconductor device is mounted.

〔発明の効果〕〔Effect of the invention〕

以上のようにこの発明によれば、予め塗布した千mペー
ストをPOBに重ね合せ転写するため、適正な半田量を
得ることが出来、かつ容易に精度の良いものが得られる
As described above, according to the present invention, since the pre-applied 1,000m paste is superimposed and transferred onto the POB, an appropriate amount of solder can be obtained, and a product with high precision can be easily obtained.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明による半導体装置の実装フローチャート
、第2図は本発明の一実施例を示す側面図、第8図は本
発明の半田シート全体図を示す斜視図、第4図は本発明
に使用される半田シート作成法の一実施例を示す側面図
及び斜視図、第5図は本発明に使用される半田シート作
成法の他の実施例を示す側面図、第6図は従来技術によ
る半導体装置の実装70−チャート、第7図はこのフロ
ーチャートに対応した各工程の斜視図及び側面図、第8
図及び第9図は一般的な半導体装置の実装状態を示すも
ので、第8図は斜視図、第9図は要部側面図である。 図中、lはプリント配線板(POB)、2&は配線パタ
ーン、4は半導体装置・5aは半田ペースト・7は半田
シート、8はフィルムである。 なお図中同一符号は同一または相当部分を示す。
FIG. 1 is a mounting flowchart of a semiconductor device according to the present invention, FIG. 2 is a side view showing an embodiment of the present invention, FIG. 8 is a perspective view showing an overall view of the solder sheet of the present invention, and FIG. 4 is a diagram showing the present invention. 5 is a side view and a perspective view showing one embodiment of the solder sheet producing method used in the present invention, FIG. 5 is a side view showing another embodiment of the solder sheet producing method used in the present invention, and FIG. 6 is a conventional technique. FIG. 7 is a perspective view and side view of each process corresponding to this flowchart, and FIG.
9 and 9 show the mounting state of a general semiconductor device, with FIG. 8 being a perspective view and FIG. 9 being a side view of the main parts. In the figure, 1 is a printed wiring board (POB), 2& is a wiring pattern, 4 is a semiconductor device, 5a is a solder paste, 7 is a solder sheet, and 8 is a film. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

【特許請求の範囲】[Claims]  半導体装置をプリント配線板に実装する場合において
、当該プリント配線板上の配線パターン上に、半田付け
するための半田を供給する方法として、半田供給部に予
め半田を塗布したシートをプリント配線板に接着し、半
田ペーストを転写法により、配線パターン上にメタルマ
スクを使用せずに、半田供給し、半田供給後にプリント
配線板より上記シートのフイルムを剥離し、その後半導
体装置を上記半田部に半田付けにより実装したことを特
徴とする半導体装置の実装方法。
When mounting a semiconductor device on a printed wiring board, as a method of supplying solder for soldering onto the wiring pattern on the printed wiring board, a sheet coated with solder in advance in the solder supply section is placed on the printed wiring board. Apply solder to the wiring pattern without using a metal mask by applying the solder paste, peel the film of the sheet from the printed wiring board after supplying the solder, and then solder the semiconductor device onto the solder area. A method for mounting a semiconductor device, characterized in that the semiconductor device is mounted by attaching the device.
JP1178418A 1989-07-11 1989-07-11 Packaging of semiconductor device Pending JPH0342894A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1178418A JPH0342894A (en) 1989-07-11 1989-07-11 Packaging of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1178418A JPH0342894A (en) 1989-07-11 1989-07-11 Packaging of semiconductor device

Publications (1)

Publication Number Publication Date
JPH0342894A true JPH0342894A (en) 1991-02-25

Family

ID=16048152

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1178418A Pending JPH0342894A (en) 1989-07-11 1989-07-11 Packaging of semiconductor device

Country Status (1)

Country Link
JP (1) JPH0342894A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008105443A1 (en) * 2007-03-01 2008-09-04 Senju Metal Industry Co., Ltd. Solder transfer sheet and solder transfer method
CN112312669A (en) * 2019-07-26 2021-02-02 北京梦之墨科技有限公司 Metal pattern, and preparation method and preparation device of metal pattern

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008105443A1 (en) * 2007-03-01 2008-09-04 Senju Metal Industry Co., Ltd. Solder transfer sheet and solder transfer method
CN112312669A (en) * 2019-07-26 2021-02-02 北京梦之墨科技有限公司 Metal pattern, and preparation method and preparation device of metal pattern

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