JPH023331B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a capacitive voltage divider circuit, and relates to a capacitive voltage divider circuit that is used, for example, in a D/A converter and improves the monotonous increase in the divided output voltage.

(2) Background of the technology In general, in a D/A converter, it is guaranteed that the output analog voltage has good linearity with respect to the input digital signal value, and that the output analog voltage increases monotonically with respect to the increase in the input digital signal value. It is important that In particular, in D/A converters that handle audio or video signals and D/A converters that use D/A converters, at least monotonous increase is guaranteed in order to maintain the similarity of the converted signal waveforms. This is required.

(3) Conventional technology and problems Conventionally, in capacitive voltage divider circuits using capacitors, 2
A plurality of capacitors weighted according to powers of are selectively connected to a reference voltage according to an input digital signal to obtain a voltage division ratio corresponding to the capacitance ratio. In this case, weighting by a power of 2 can be achieved by configuring a capacitance with an area corresponding to each capacitance value or by connecting in parallel unit capacitances equal to the minimum capacitance, but the former method is based on a capacitance pattern Because of its high process dependence, it is rarely used at present. Considering the latter method, even in this method, the error increases with heavily weighted capacitances due to errors in individual unit capacitances. For example, in the case of 6 bits, the capacity of 2 ⁶ = 64 pieces is given by C ₀ as the unit capacity.
It is divided into 32C ₀ , 16C ₀ , 8C ₀ , 4C ₀ , 2C ₀ , C ₀ , and C ₀ and weighted. In this case, the capacity is 31C ₀ (=16C ₀
When changing from +8C ₀ +4C ₀ +2C ₀ +C ₀ ) to 32C ₀ , the error becomes the largest because all the capacitances connected to the reference voltage change. A particular problem here is monotony. In other words, the sum of all capacities is
If C _T , then C _T =32C ₀ +16C ₀ +8C ₀ +4C ₀ +2C ₀ +C ₀ +C ₀ ...(1), and further assuming that the error of C _T is zero, ΔC ₀ +ΔC ₁ +ΔC ₂ +ΔC ₄ +ΔC ₈ +ΔC ₁₆ +ΔC ₃₂ =0 (2). Furthermore, if the cumulative error from 16C ₀ to C ₀ is ΔC ₃₁ , then the error when 31C ₀ is selected is ΔC ₃₁ . Furthermore, since C _T = 32C ₀ + 31C ₀ + C ₀ = 32C ₀ + C ₀ + (31C ₀ + ΔC ₃₁ ) − ΔC ₃₁ …(3), the error when 32C ₀ is selected is the error of C ₀ and the error of −ΔC ₃₁ . Become peace. Therefore, from 31C ₀
The error when changing to 32C ₀ becomes 2ΔC ₃₁ if the error ΔC ₀ of C ₀ is ignored. If ΔC ₃₁ > (1/2)C ₀
If 31C ₀ + ΔC ₃₁ > 31C ₀ + (1/2)C ₀ = 31.5C ₀ 32C ₀ −ΔC ₃₁ <31.5C ₀ , the voltage value is reversed. This is called monotonically increasing property not being satisfied. That is, such a voltage divider circuit has a drawback that the monotonous increase property tends to be broken when switching the large capacitance of the bits mentioned above.

Next, explanation will be given using the specific example shown in FIG. 1st
The figure shows a conventional voltage divider circuit in which the first voltage
The output voltage V ₀ is obtained by dividing the voltage between V ₁ and the second voltage V ₂ using capacitors. SW ₁ to SW ₆ are changeover switches, and have capacitances C ₀ , 2C ₀ , 4C _{0 ,} weighted according to the values of the first to sixth bits of the input digital signal, respectively.
One end of 8C ₀ , 16C ₀ , and 32C ₀ is connected to voltage V ₁ or V ₂ by switching. The transistor TD is used to charge each capacitor C ₀ to 32C ₀ to a predetermined potential before voltage division operation, and each switch SW ₁ to SW ₄ is all connected to, for example, the voltage V 2 side, and the voltage V is connected to the voltage V ₂ side, for example. It is set to V ₁ and turned on for a short time by the clock CLK. Therefore, the circuit of FIG. 1 operates as a D/A converter that converts a 6-bit input digital signal into a corresponding analog signal.

In the circuit shown in Figure 1, if the average value of unit capacitance C ₀ is ₀ , then 31C ₀ = 31 ₀ + ΔC ₁ + ΔC ₂ + ΔC ₄ + ΔC ₈ + ΔC ₁₆ ...(4) 32C ₀ = 32 ₀ + ΔC ₃₂ ...(5) From these formulas, the capacitance change when the input digital signal changes from “011111” to “100000” is 32C ₀ −31C ₀ = ₀ +ΔC ₃₂ −(ΔC ₁ +ΔC ₂ +ΔC ₄ +ΔC ₈ +ΔC ₁₆ )… (6), and using the above equation (2), 32C ₀ −31C ₀ = ₀ −ΔC ₀ −2 (ΔC ₁ +ΔC ₂ +ΔC ₄ +ΔC ₈ +ΔC ₁₆ ) …(7). At this time, ΔC ₀ +2 from the second term onwards in equation (7)
If (ΔC ₁ +ΔC ₂ +ΔC ₄ +ΔC ₈ +ΔC ₁₆ ) is larger than ₀ , the monotonic property is not satisfied.

Also, when the input digital signal changes from “001111” to “010000”, 16C ₀ −15C ₀ = ₀ + ΔC ₁₆ − (ΔC ₁ + ΔC ₂ + ΔC ₄ + ΔC ₈ ) …(8), and the above equation (6) Since the number of unit capacitances used is smaller than the error in the amount of change in , the accumulated error is generally considered to be smaller. That is, switching of the upper bits is more susceptible to element errors.

Therefore, the conventional type has the disadvantage that the monotonous increase property tends to break down especially when the capacitance of the upper bit is switched.

(4) Purpose of the Invention The purpose of the present invention is to solve the above-mentioned problems with the conventional type, and to develop a voltage dividing circuit based on the concept of dividing the weighting capacitance corresponding to the upper bit into a plurality of capacitances. The object of the present invention is to prevent monotonicity from being destroyed due to errors in weighted capacitances, and to improve resolution without being affected by element errors.

(5) Structure of the Invention According to the present invention, a plurality of capacitors each having a capacitance value weighted to a power of 2 and a switch connected to each capacitor are provided, and the switch is operated according to an input digital signal. Selectively set each capacity to the first or second
is connected to the voltage terminal of the first
and a capacitor voltage divider circuit that divides the voltage between the second voltage terminals, in which at least the capacitor corresponding to the most significant bit among the plurality of capacitors is constituted by two partial capacitors having equal capacitance values; When two partial capacitors are connected to the first or second voltage terminal by the switch, and the input digital signal switches from a state where only the most significant bit is "0" to a state where only the most significant bit is "1". Then, the weighted capacitance value for the most significant bit is one of the two partial capacitances corresponding to the most significant bit.
A capacitor voltage divider circuit is provided, characterized in that the switch is controlled so that one of the two capacitors is combined with a capacitor corresponding to a bit one bit lower than the most significant bit. .

(6) Embodiments of the invention Examples of the invention will be described below with reference to the drawings.
FIG. 2 shows a voltage divider circuit according to one embodiment of the present invention. In Figure 2, the capacity 32C ₀ in Figure 1 is 2
It is divided into _{16C 0 (} 2) and 16C ₀ (3) with a capacity of 16C 0, and therefore, together with the capacity 16C ₀ (1), a total of three 16C ₀ capacities are used, and each switch SW ₇ ，
Connected to voltage V ₁ or V ₂ by SW ₈ and SW ₉ . Furthermore, a gate circuit having an OR gate OG1 and an AND gate AG1 is used to control these switches _SW7 , _SW8 , and _SW9 .
Other points are the same as the voltage dividing circuit shown in FIG.

In the circuit shown in Figure 2, for example, when the input signal is "011111", the capacitances C ₀ , 2C ₀ , 4C ₀ , 8C ₀ ,
16C ₀ (1) is connected in parallel to the voltage V ₁ to form a capacitor 31C ₀ . Next, when the input signal changes to "100000", capacitors 16C ₀ (1) and 16C ₀ (2) connected to switches SW ₇ and SW ₈ are connected in parallel to voltage V ₁ , and capacitor 32C ₀ configured. In other words, the capacity is
Even when changing from 31C ₀ to 32C ₀ , since the capacitance 16C ₀ (1) is included in common, the monotonous increase property is improved.

From 31C ₀ in the same way as in the conventional example above
Considering the case where it changes to 32C ₀ , 32C ₀ = 16C ₀ (1) + 16C ₀ (2) …(9) 31C ₀ = C ₀ +2C ₀ +4C ₀ +8C ₀ +16C ₀ (1) …(10), so 32C ₀ −31C ₀ = ₀ +ΔC ₁₆ (1)+ΔC ₁₆ (2)− {ΔC ₁ +ΔC ₂ +ΔC ₄ +ΔC ₈ +ΔC ₁₆ (1)} = ₀ +ΔC ₁₆ (2)− (ΔC ₁ +ΔC ₂ +ΔC ₄ +ΔC ₈ )
…(11) becomes. Therefore, the equation becomes the same as the case of the capacitance change of one bit lower than that shown in equation (8) above, that is, the case of changing from 15C ₀ to 16C ₀ , and the cumulative error due to capacitance switching becomes small.

In FIG. 3, in addition to the most significant bit MSB, the capacity of the lower bits is also divided.
In the figure, the capacitance C ₁₆ (1) in Figure 2 is replaced by C ₈ (2), C ₈
(3), each capacity 8C ₀ (1) to 8C ₀ (3) and
16C ₀ (1) and 16C ₀ (2) respectively with switch SW ₁₀ or
Switch and connect using SW ₁₄ . Further, each of these switches _SW10 to _SW14 is controlled by a gate circuit composed of OR gates OR2, OR3 and AND gates AG2, AG3. According to the configuration shown in FIG. 3, the error during capacity switching is reduced compared to the configuration shown in FIG.
Furthermore, it can be reduced to a value corresponding to the one-bit lower capacity switching.

Note that in the circuits shown in FIGS. 2 and 3, the transistor TD forms a charge/discharge switch as described above, and is connected to a predetermined sampling clock.
Turned on or off by CLK. When the transistor TD is on, the output potential _V0 is set to a constant potential _V1 , and the input digital signal is set to a constant value such as all "0" or all "1", so that the initial value accumulated in each capacitor is It works to keep the electric charge constant. The transistor TD is turned off during a period in which the analog signal voltage is output.
In addition, by changing each bit of the input digital signal according to the next input digital signal during charging and discharging, that is, when the transistor TD is on, the error in the output voltage is automatically corrected by changing the initial charge to a value according to the input digital signal. It is also possible to make a correction.

The voltage dividing circuit according to the present invention includes a D/A converter, an A/
Can be used for D converters or switched capacitor filters, especially D/A and A/D
Excellent effects can be obtained in the case of transducers.

(7) Effects of the Invention According to the present invention, a plurality of capacitors each having a capacitance value weighted to a power of 2 and a switch connected to each capacitor are provided, and each capacitor is controlled by the switch according to an input digital signal. In a capacitor voltage divider circuit that selectively connects a capacitor to a first or second voltage terminal and divides the voltage between the first and second voltage terminals according to a charge redistribution law, one of the plurality of capacitors is , the capacitor corresponding to at least the most significant bit is constituted by two partial capacitors having equal capacitance values, and the two partial capacitors are connected to the first or second voltage terminal by the switch; When the input digital signal switches from a state where only the most significant bit is "0" to a state where only the most significant bit is "1", the capacitance value weighted to the most significant bit is 2 a capacitive voltage divider circuit that controls the switch so that one capacitance of one of the partial capacitors is combined with a capacitance corresponding to a bit one bit lower than the most significant bit; provided.

Therefore, the conventional inconvenience in which the monotonous increasing property is broken due to the error in the weighted capacitance by the device shown in FIG. The advantage is that the resolution can be improved without being affected.

[Brief explanation of drawings]

FIG. 1 is a schematic electrical circuit diagram showing a conventional capacitive voltage divider circuit, and FIGS. 2 and 3 are schematic electrical circuit diagrams showing a capacitive voltage divider circuit according to an embodiment of the present invention. C ₀ , 2C ₀ , 4C ₀ , 8C ₀ , 16C ₀ , 32C ₀ …Capacity,
SW ₁ , SW ₂ ,…SW ₁₄ …Switch, OG1, OG2,
OG3...OR gate, AG1, AG2, AG3...AND gate, TD...Charging/discharging transistor.

Claims (1)

[Claims] 1. It has a plurality of capacitors having capacitance values weighted to powers of 2 and a switch connected to each capacitor, and the switch selectively sets each capacitor to the first or second level according to the input digital signal. In a capacitor voltage divider circuit that is connected to a voltage terminal and divides the voltage between the first and second voltage terminals according to the charge redistribution law, among the plurality of capacitors, at least the capacitor corresponding to the most significant bit has a phase difference. It is composed of two partial capacitors having the same capacitance value, and the two partial capacitors are connected to the first or second voltage terminal by the switch, and the input digital signal has only the most significant bit set to "0". When switching from the state where only the most significant bit is "1", the capacitance value weighted to the most significant bit is equal to the capacitance of one of the two partial capacitances corresponding to the most significant bit. ,
A capacitive voltage dividing circuit characterized in that the switch is controlled so that the most significant bit is combined with a capacitor corresponding to a bit one bit lower than the most significant bit.