JPH0577219B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an A/D (analog/digital) conversion circuit, and in particular to a resistor string type D/A conversion circuit that achieves high integration and high speed of component circuits. The present invention relates to an A/D conversion circuit using a semiconductor integrated circuit which is miniaturized by sharing the upper bits with a charge distribution type D/A converter with a plurality of parallel capacitors and sharing the lower bits.

[Conventional technology]

FIG. 2 is a circuit diagram showing a conventional example of an A/D conversion circuit. A so-called resistor string type D/A converter uses a comparison voltage obtained by dividing the reference potential V _REF by resistors R _{0 to} B _o , and a capacitor group (conventionally In the example C ₁₀
×2 ⁰ = C ₁₁ , C ₁₀ ×2 ¹ = C ₁₂ ).
The converter converts the upper bit, and the charge redistribution type D/A
The converter takes charge of the lower bits and the comparator OP
11 and gate circuit G11, the inputs are successively compared and finally a desired A/D conversion value is obtained.

Each timing will be explained in more detail.
First, switch _S10 closes to bias the input to the comparator level of comparator OP11. At this time, switches S ₁₁ , S ₁₂ , and S ₁₄ are switched to connect with analog input V _io . This is the sample-and-hold timing, and the analog input V _io is held between capacitors C ₁₀ , C ₁₁ , and C ₁₂ .

Next, switch S ₁₀ opens, switches S ₁₁ and S ₁₂ remain as they are, and switch S ₁₄ becomes the resistor string type D/A.
Select the converter side. At this time, the first switch group SW ₁₀
selects V _REF × 1/2 and compares it with the analog value V _io held between capacitors C ₁₀ , C ₁₁ , and C ₁₂ and comparator OP11.
If the comparison is made by , then the switch group is
A so-called binary search is performed using V _REF × 3/4, or if it is smaller, V _REF × 1/4. In these cases, the output of comparator OP11 is gate circuit G1.
Switch group immediately before passing through 1 and performing the next comparison
This is executed by switching _SW10 .

Once the upper bits are determined in this way, a more detailed search is then performed on the charge redistribution type D/A converter side. That is, if the output of the comparator OP11 is high, the switch _S14 switches to a lower potential than the switch _S13 , and at the same time, the switch _S12 switches to the switch _S13 side. As a result, a level that is 1/2 of the minimum level obtained on the resistor string type D/A converter side is added. Furthermore, if the output of comparator OP11 is high, the LSB (least significant bit)
The switch _S11 that determines the switch S13 becomes the switch _S13 , and the output of the comparator OP11 at that time determines the LSB.
Of course, these switches _S11 to _S14 are gate circuits G.
It is controlled by 11.

[Problem that the invention seeks to solve]

In the conventional A/D conversion circuit described above, the switch group must be divided into two and alternately connect one side to the resistor string type D/A converter and the other side to the charge redistribution type D/A converter side. It won't happen. For this reason,
The arrangement of the resistor string type D/A converter section becomes complicated, and a large number of switches are required for each capacitor that holds an analog value, and the on-resistance and parasitic capacitance of these switches limit the operating speed of the A/D conversion circuit. There is a drawback that it does.

[Means for solving problems]

The A/D conversion circuit of the present invention connects an analog input and a resistor string type D/A converter to the first input terminal of the comparator to determine the upper bit in A/D conversion, and determines the upper bit in the A/D conversion. 2
A successive approximation type A/A converter that determines the lower bit in A/D conversion by connecting a charge redistribution type D/A converter with multiple capacitors in parallel to the input terminal of the converter.
In the D conversion circuit, a first switch connected to the analog input is connected to the first input terminal of the comparator through an input capacitor, and the first reference potential is divided by a plurality of resistors in preset step widths. Each node potential of the circuit is connected through the switch group and the input capacitor, and a third switch having a minimum unit capacitance is connected in parallel to the second input terminal, and a third switch is connected in parallel with the second reference potential. connected first capacitors, each having a capacitance that is a power of 2 times the capacitance of the first capacitor, and each having a difference from the second reference potential to the second reference potential. connecting in parallel a plurality of second capacitors that are switched and connected to either a third reference potential or a fourth reference potential that is equal to the minimum value set by the step width of the reference potential of the resistor and differs only in polarity; While comparing the potentials generated by the first capacitor and the plurality of second capacitors using each node potential of the plurality of resistors as a reference voltage, the resistor string-type D/A converter and the charge regeneration are performed. This configuration performs A/D conversion based on parallel operation with a distributed type D/A converter.

〔Example〕

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention. A so-called resistor string type D/A converter in which the first reference potential V _REF is divided by resistors r ₀ to r _o , and a group of capacitors having a relationship of a unit capacitor (capacitor) C ₀ to a power of 2 (in the embodiment C ₀ ×2°=C ₁ , C ₀ ×2 ² =
It is a combination of so-called charge redistribution type D/A converters configured with _C2 ), in which the resistor string type D/A converter converts the upper bits, and the charge redistribution type D/A converter converts the lower bits. A desired A/D conversion value is finally obtained while successive comparison is performed between the comparator OP1 and the gate circuit G1.

The basic configuration up to this point is almost the same as the conventional example. Next, each timing will be explained in more detail. First, switch _S3 closes to bias the input to the comparator level.

At this time, the first switch _S4 is also closed and the analog input Vin is stored in the capacitor Cin. At this time, the switches S ₁ and S ₂ forming the second switch group SW ₂ are
is connected to the common reference potential of the second switch.
_S0 is also closed, and the common level of comparator OP1 is determined.

Next, the switches S ₁ , which constitute the second switch group,
As for S ₂ , switches S ₀ , S ₃ , and S ₄ are opened, and switch group SW ₁ as the first switch group becomes a comparator.
The output of OP1 passes through gate circuit G1 and is switched to perform a binary search.

Once the upper bits are determined in this way, a more detailed search is performed by changing the common level using a charge redistribution type D/A converter connected to the common side of the comparator OP1. That is, if the output of comparator OP1 is high, switch _S2 selects the third reference potential, common +, which is higher than common. Here, common + is a voltage higher than common by the voltage of the minimum step selected by the resistor string type D/A converter, and common - as the fourth reference potential is vice versa. In addition,
These voltages are taken directly from the resistor string type D/A converter. This way the comparator
The common of OP1 becomes a level 1/2 higher than the minimum level obtained by the resistor string type D/A converter and is compared with the input Vin. If the output of comparator OP1 is still high after that, switch _S1
It becomes the common + side, and as a result, A/D conversion is completed.

In this explanation, the charge redistribution type D/A converter requires three potential commons, 2nd to 4th, common + and common -, but the common connected to capacitor C ₀ etc. uses a switch. If the polarity is switched to take two values, only two reference potentials are required. FIG. 3 is a circuit diagram for explaining the improvement of the charge redistribution type D/A. By adding switch _S23 , you can switch the polarity in the same way as connecting to common + and common -. The difference between common + and common - is common +
It is the same as the difference between common and common, and common and common.

In this way, by using the level divided by the resistor as a reference and comparing the level generated by the capacitor, the resistor string type D/A
D/D in the form of charge redistribution using a converter and multiple capacitors
The linked operation of the A converter can be changed from the conventional series operation to parallel operation, and the conventional system requires two types of switch groups to generate divided levels using resistors. In addition to greatly reducing the occupied area, it is also possible to significantly speed up the operation by eliminating the need for driving the charge redistribution type D/A converter with a resistor string type D/A converter.

〔Effect of the invention〕

As explained above, the present invention connects a resistor string type D/A converter to the first input terminal of a comparator in an A/D conversion circuit to share the upper bits in A/D conversion, and also A charge redistribution type D/A converter with multiple capacitors connected in parallel is connected to the second input terminal.
By sharing the lower bits in D conversion and making it possible for these two D/A converters to operate in parallel, the resistor string type D/A
This has the advantage that the output decoder of the converter can be integrated into one system, resulting in high integration. Furthermore, since the number of output decoders is reduced, the on-resistance and parasitic capacitance of the switch are also reduced, which has the advantage of increasing the speed.

[Brief explanation of drawings]

Figure 1 is a circuit diagram of an embodiment of the present invention, Figure 2 is a circuit diagram of a conventional A/D conversion circuit, and Figure 3 explains improvements to the charge redistribution type D/A converter. FIG. S ₀ ~ S ₄ , S ₁₀ ~ S ₁₄ , S ₂₀ ~ S ₂₃ ... Switch,
SW ₁ , SW ₂ , SW ₁₀ ... Switch group, Cin, C ₀ ~
C ₂ , C ₁₀ ~ C ₁₂ , C ₂₀ ~ _{C 22} ... Capacitor, r ₀ ~ _{r o} ,
R ₀ ~R _o ...Resistor, OP1, OP11...Comparator, G1, G11...Gate circuit.

Claims (1)

[Claims] 1. An analog input and a resistor string type D/A converter are connected to the first input terminal of the comparator to determine the upper bit in A/D conversion, and the second input terminal of the comparator In a successive approximation type A/D conversion circuit that determines lower bits in A/D conversion by connecting a charge redistribution type D/A converter with a plurality of parallel capacitors to a terminal, the first input of the comparator A first switch connected to the analog input is connected to the terminal through the input capacitor, and the potential at each node of the circuit, which is obtained by dividing the first reference potential by a plurality of resistors in increments set in advance, is connected to the switch group and the input. A first capacitor having a minimum unit capacitance is connected to the second input terminal through a capacitor, and a second switch is connected in parallel to the first capacitor and a second reference potential is connected to the first capacitor. Each capacitor has a capacitance that is a power of 2 times the capacitance of the first capacitor, and each of the capacitors is set at the second reference potential or the difference from the second reference potential is set in steps of the first reference potential by the resistance. a third reference potential that is equal to the minimum value that differs only in polarity, and a fourth reference potential that is equal to the minimum value of
A plurality of second capacitors which are switched and connected to one of the reference potentials are connected in parallel, and each node potential of the plurality of resistors is used as a reference voltage by the first capacitor and the plurality of second capacitors. A/D conversion is performed based on parallel operation of the resistor string type D/A converter and the charge redistribution type D/A converter while comparing generated potentials. D conversion circuit.