JPH02352A - Manufacture of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To enable the use of a mask of rough pattern accuracy by a method wherein a plurality of impurity introducing holes are formed by etching an SiO2 film on an epitaxial layer, and then impurity is introduced by using a resist film as a mask and by selecting introducing holes for ion implantation. CONSTITUTION:After a silicon oxide film 26 is formed on an epitaxial layer 23, a resist pattern 27 is formed on the silicon oxide film 26; by using the resist pattern 27 as a mask, the above oxide film 26 is etched and an oxide film pattern 26 is formed; a plurality of impurity introducing holes are formed at the same time. In the state where the resist pattern 27 is left, first boron is implanted, and a resistive region 28 and the base region 29 of an NPN transistor are formed on two islands 25. After the resist 27 is eliminated, resist films 30, 31 are formed on the above oxide film 26. By using these films as masks, second boron is implanted in the above introducing holes to form a contact region 32.

Description

[Detailed Description of the Invention] (Field of Industrial Application) The present invention facilitates the control of NPN transistors in a semiconductor integrated circuit incorporating a resistance element formed by ion implantation, and greatly improves the integration density. The present invention relates to a method for manufacturing a semiconductor integrated circuit.

(b) Conventional technology A bipolar IC is mainly composed of a vertical NPN transistor formed by doubly diffusing a base and an emitter on the surface of a semiconductor layer serving as a collector. Therefore, the base and emitter diffusion processes for manufacturing the NPN) transistors are essential processes, as well as the high-concentration buried layer formation process and epitaxial layer growth process to reduce the collector series resistance, and the junction separation of each element. This is an indispensable process (basic process) for manufacturing bipolar ICs, along with the isolation region formation process for electrical connection and the electrode formation process for electrical connection.

On the other hand, due to circuit requirements, there is a demand for incorporating other elements such as PNP transistors, resistors, capacitors, Zener diodes, etc. on the same substrate. In this case, it goes without saying that it is preferable to utilize the basic steps as much as possible in terms of process simplification. However, since the conditions for the base and emitter diffusion steps are set with the most important consideration being given to the characteristics of the NPN transistor, it is often difficult to integrate the base and emitter diffusion steps using only the basic steps.

Therefore, a new process may be added not for the purpose of forming a basic NPN transistor, but for the purpose of incorporating other elements or improving the characteristics of other elements.

For example, the P1 diffusion process to form an anode region that controls the Zener voltage of the Zener diode with the cathode region by the emitter diffusion, the R diffusion process to form a resistance region with a different resistivity from the base region, and the implant resistance. These include the formation process, the nitride film formation process to form a nitride film capacitor that provides a larger capacitance than the MOS type, and the collector low resistance region formation process to further reduce the collector series resistance of the NPN transistor. This is a process (optional process) in which it is determined whether to add an IC based on consideration of the use, purpose, and cost of the IC.

The implant resistor formed using the above optional process is shown in FIG. 3. In the figure, (1) is a P-type semiconductor substrate, (2) is an N+ type buried layer, (3> is an N-type epitaxial layer, (4) is a P" type separation region, (5) is an island, (
6) is the P-type base region of the NPN transistor, (7) and (8) are the N1-type emitter region and collector contact region of the NPN transistor, (9) is the resistance region by ion implantation, and (10) is the base diffusion region. This is the formed contact area.

For example, the implant resistance shown in Figure 3 is
As described in Japanese Patent No. 182, it was formed after emitter diffusion.

(c) Problems to be solved by the invention However, after the emitter region (7) is formed, the resistance region (
9) Forming NPN l-transistor glue.

(current amplification factor) is heat treated to control the resistance region (
9) Must be done after formation. Then, the heat treatment at several hundred degrees Celsius performed before the photoetching of the resistor region (9) causes the emitter region (7) to diffuse, resulting in large variations in the thickness of the NPN transistor, which has the disadvantage of being difficult to control. .

Also, the emitter area (
Since it is necessary to change the heat treatment conditions in 7), process control is required for each model, and there is a drawback that control cannot be standardized.

Furthermore, a plurality of diffusion regions (6), (9), (10
), etc., there are photoresist coating, mask alignment, exposure, development, and photoetching steps before each diffusion process, and deviations from design values occur in the mask alignment process. This misalignment causes the diffusion regions to come into contact with each other, and a margin of several μm was provided within the film to prevent this misalignment. Therefore, an increase in the degree of integration was prevented.

(d) Means for Solving the Problems The present invention has been made in view of the above-mentioned problems, and includes a step of forming a silicon oxide film (26) on an epitaxial layer (23), and etching the silicon oxide film (26). a step of forming a plurality of impurity introduction holes, and a step of forming the silicon oxide film (26
) with the resist film (27) applied as a mask,
A step of selectively introducing impurities into the introduction hole, and a resist film (30) on the silicon oxide film (26);
31), and the resist film (30),
The solution is to include at least the step of selectively introducing impurities into the introduction holes using (31) as a mask.

(E) Function In the present invention, a plurality of introduction holes are formed with high precision in the dinocon oxide film (26) on one end of the epitaxial layer (23), and then the openings in the resist film are made wider than the introduction holes. For example, the position of the diffusion region can be determined by the formation position of the introduction hole.

Therefore, even if the formation position of the resist film is rough and the opening position shifts in the direction of spreading, the formation position of the diffusion region can be formed with high precision, so the conventional margin is completely unnecessary, and the degree of integration can be improved. .

(F) Example Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

First, as shown in FIG. 1A, a P-type silicon semiconductor substrate (
N-type impurities such as antimony (Sb) or arsenic (As) are selectively added to the surface of the N+ type buried layer (22).
), and an N-type epitaxial layer (23) with a thickness of 5 to 10 μm is laminated on the entire surface of the substrate (21).

Next, as shown in FIG. 1B, by selectively diffusing boron (B) from the surface of the epitaxial layer (23),
Epitaxial layers (
A P+ type isolation region (24) is formed passing through (23). an epitaxial layer (23) surrounded by an isolation region (24);
) is an island (25) for forming each circuit element.
becomes.

Next, as shown in FIG.
A positive type photoresist is applied on the oxide film (26) by spin-on coating, and then a desired photoresist is applied using an exposure apparatus having an overlay accuracy of 1 μm or less, such as a reflection projection method or a reduction projection exposure method. A first resist pattern (27) having a plurality of overlapping openings is formed by baking and developing a shaped pattern.

Next, as shown in the first diagram, the oxide film (26) is anisotropically etched by dry etching such as reactive ion etching to form the first resist pattern (26).
An oxide film (26) pattern corresponding to step 7) is formed, and a plurality of impurity introduction holes are formed at once.

After that, with the first resist pattern (27) remaining as a mask, the first boron (B) ion implantation is performed from the epitaxial Jul (23) surface to give the same impurity concentration to the two island (25) surfaces. A resistance region (28) and a base region (29) of an NPN transistor are respectively formed. In the first ion implantation, the boron (B) dose t and acceleration voltage are selected in accordance with the impurity concentration of the resistance region (28) on the side where the resistivity is to be increased.

Next, as shown in FIG. 1E, the first resist pattern (
27) is removed, a negative photoresist film is spin-on coated on the surface, and a pattern of a desired shape is printed using a proximity exposure method or a projection exposure method, and developed to create a second resist pattern ( 30). Second resist pattern (30
) has a smaller shielding portion than the first resist pattern (27), and a second resist film (30) is formed on the region where ions are not implanted.

Therefore, in the opening part of the second resist pattern (30), one surface of the region ion-implanted in the previous step and the oxide film (
26) Edges of the pattern will be exposed. Also, a part (31) of the second resist pattern (30)
directly covers the surface of the resistive region (28> except for both ends), exposing only the contact portion of the resistive region (28).

Here, since the introduction hole with precision is formed in advance,
As mentioned above, without considering the accuracy of the second resist pattern, the base region (2
9) can be determined as described below.

Next, as shown in the first step, a second boron (B) ion implantation is performed from the surface of the epitaxial layer (23) using the oxide film (26) pattern formed in the previous step as a mask again. Boron (B) is ion-implanted into the base region (29) of the NPN transistor in a layered manner with high accuracy, so at this stage a second ion implantation is performed to determine the impurity concentration on the side that lowers the resistivity, that is, the base region (29). The implant dose is set. In addition, the impurity concentration of the base region (29) is set to such an impurity concentration that ohmic contact can be made with the electrode that will be formed later, and a second ion implantation is also performed at both ends of the resistance region (28). A contact region (32) for electrode arrangement having the same impurity concentration as (29) is formed.Contact region (32)
The resistance region (28) between
0), the second boron (B) ion implantation is not performed. Therefore, the impurity concentration of the part covered by the part (31) of the second resist pattern (30) remains the same as the impurity concentration set by the first ion implantation, and this region increases the resistance value of the implant resistor. This is the area that will essentially be determined. Furthermore, since the impurity concentration is low, the contact region (32) described above is required. Thereafter, the resist pattern (30) is removed for the second time, the entire structure is covered with a CVD oxide film (26), and a heat treatment is performed to diffuse the base region (29) to a certain depth.

Incidentally, since the edge portion of the oxide film (26) is completely exposed and this oxide film (26) is used as a mask, it is necessary to form, for example, a thick silicon oxide film of approximately 7,000 layers in the process shown in Figure 1C. be.

Therefore, since highly precise impurity introduction holes are formed in the first planning process, the two ion implantations in the base region overlap with high precision, and the openings in the second resist pattern are simply Since it is sufficient to form the hole wider than the introduction hole, the accuracy may be rough.

Next, as shown in FIG. 1G, holes are formed in the oxide film (26) on the surface of the base region (29) and the surface of the island (25) of the NPN transistor, and using this oxide film (26) as a mask, phosphorus (P) is added. Immediately after removing the glass film, heat treatment is applied in an oxidizing or non-oxidizing atmosphere, and phosphorus (P) is driven in to form the emitter region (33) and collector contact region (34) of the NPN l-transistor. ) to form. NP at the drive-in of this process
N Controls hFll (current amplification factor) of the transistor.

Next, as shown in the first step, a contact hole is formed by etching a predetermined portion of the oxide film (26), and then an aluminum layer is formed on the entire surface of the epitaxial layer (23) by a well-known vapor deposition or sputtering technique. , by patterning this aluminum layer, electrodes (3
5).

A plan view of the implant resistor formed by the above manufacturing method is as shown in FIG. In the same figure, (25) is an island, (28) is a resistance region, (32) is a contact region,
(36) is Hung Takt Hall, Sori, Tae (31) is the first
The shape of a part of the second resist pattern (3o) in the second resist pattern is shown. Since the line width of the resistance region (28) and the size of the contact region (32) are already determined by the first resist pattern (27) in FIG. Part (31) of the second resist pattern (30), not the distance between
is determined by the length of the resistive region (28) covered by the resistor region (28). Therefore, in this embodiment, the size of the contact hole (36) is
By making the line width less than or equal to 8), the contact area (3)
By adopting this structure, the side edge (37) of the portion (31) of the second resist pattern (30) is used as the contact region (32). It is aligned with the side edge (38) of. Therefore, the area occupied by the implant resistor can be minimized, fluctuations in resistance value due to mask displacement can be slightly ignored, and the base region (29) can be manufactured with the same high precision as the implant resistor.

According to the manufacturing method of the present application described above, the emitter region (33
) Before forming the resistive region (28), ion implantation is performed to form the resistive region (28), so phosphorus (P) for forming the emitter region (33) is used.
After depositing the hFI of the NPN transistor immediately without placing any extra heat treatment! You can move to a drive-in for control. Therefore, NPN
There is little variation in transistor hyt (current amplification factor), and hFI is achieved by incorporating an implant resistor! It can eliminate the difficulty of control. In addition, the emitter region (33) regardless of whether an implant resistor is incorporated or not.
Since the heat treatment conditions can be unified, process management for each model becomes easier.

Furthermore, a plurality of introduction holes are formed in the oxide film (26) at one end, and ion implantation is performed multiple times later in the edge portion of the oxide film (26), so that the resistive region (28) and the base region (
29), the formation position can be determined at this edge portion. Therefore, the pattern accuracy of the second resist film (30) only needs to be wider than the introduction hole, so it may be rough. Therefore, there is no need to consider mask displacement in FIG. 1F.

(g) As described in detail of the invention, a plurality of introduction holes are formed by etching the upper silicon oxide film, and then impurities are implanted by selecting the introduction holes for ion implantation using the resist film as a mask. Once introduced, the formation position of the diffusion region can be determined at the edge portion of the selected introduction hole.

Furthermore, since it is sufficient to form a resist film that is wider than the introduction hole, the pattern accuracy may be rough, and there is no need to consider displacement of the resist film at all.

Therefore, since there is no need to provide a margin for this mask shift, the degree of integration can be improved accordingly.

Next, the silicon oxide film corresponding to the intended base region and intended resistance region on one end of the epitaxial layer is etched to form respective introduction holes, and then the introduction holes for ion implantation are selected using the resist film as a mask. Then, by introducing impurities, the formation positions of the base region and the resistance region can be determined at the edge portion of the selected introduction hole.

Furthermore, since it is sufficient to form a resist film that is wider than the introduction hole, the pattern accuracy may be rough, and there is no need to consider displacement of the resist film at all.

Therefore, since there is no need to provide a margin for this mask shift, the degree of integration can be improved accordingly. Moreover, when forming the introduction hole, if the separation distance between the separation region and the base region is taken into consideration, the base region will not be misaligned, and the base region will move closer to the separation region. The problem of deterioration of characteristics can be eliminated.

[Brief explanation of the drawing]

1A to 1H are sectional views for explaining the present invention, FIG. 2 is a plan view for explaining the present invention, and FIG. 3 is a sectional view for explaining a conventional example. .

Claims (3)

[Claims] (1) A step of forming a silicon oxide film on the epitaxial layer, a step of etching the silicon oxide film to form a plurality of impurity introduction holes, and using a resist film coated on the silicon oxide film as a mask. , a step of selectively introducing an impurity into the introduction hole, a step of applying a resist film on the silicon oxide film, and a step of selectively introducing an impurity into the introduction hole using the resist film as a mask. A method for manufacturing a semiconductor integrated circuit, comprising at least the following. (2) forming a silicon oxide film on the epitaxial layer; etching the silicon oxide film corresponding to at least the base region of the intended transistor and the intended resistance region to form a plurality of impurity introduction holes; selectively introducing impurities into the introduction hole using a resist film applied on the silicon oxide film as a mask; applying a resist film on the silicon oxide film; using the resist film as a mask; A method for manufacturing a semiconductor integrated circuit, comprising the step of selectively introducing an impurity into the introduction hole. (3) forming a plurality of buried layers of opposite conductivity type on a semiconductor substrate of one conductivity type; forming an epitaxial layer of opposite conductivity type on the semiconductor substrate; and separating the epitaxial layer. forming a plurality of islands; forming a silicon oxide film on the epitaxial layer; and etching the silicon oxide film corresponding to at least the base region of the intended transistor and the intended resistance region to form a plurality of impurities. a step of forming an introduction hole; a step of selectively introducing an impurity into the introduction hole using a resist film coated on the silicon oxide film as a mask; and a step of applying a resist film on the silicon oxide film. , selectively introducing an impurity into the introduction hole using the resist film as a mask; diffusing the base region formed by introducing the impurity to a predetermined depth; and base region on the surface of the epitaxial layer. A method of manufacturing a semiconductor integrated circuit, comprising the step of: forming an emitter region of the transistor by diffusing impurities into the semiconductor integrated circuit.