JPH0236552A - Integrated circuit device - Google Patents
Integrated circuit deviceInfo
- Publication number
- JPH0236552A JPH0236552A JP63187224A JP18722488A JPH0236552A JP H0236552 A JPH0236552 A JP H0236552A JP 63187224 A JP63187224 A JP 63187224A JP 18722488 A JP18722488 A JP 18722488A JP H0236552 A JPH0236552 A JP H0236552A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- lead frame
- circuit device
- deflection
- circuit element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/884—Die-attach connectors and bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Lead Frames For Integrated Circuits (AREA)
- Credit Cards Or The Like (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、ICカード等に用いられる集積回路装置に関
するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to an integrated circuit device used in IC cards and the like.
従来の技術
近年、マイクロコンピュータ−、メモリ等の集積回路素
子をプラスチック裂カードに搭載または埋設したいわゆ
るICカードが実用に供されつつある。2. Description of the Related Art In recent years, so-called IC cards, in which integrated circuit elements such as microcomputers and memories are mounted or embedded in plastic cards, have been put into practical use.
このICカードは、すでに多量に使用されている磁気ス
トライプカードに比して記憶容量が大きく、防犯性に優
れていることから、従来の磁気ストライプカードの用途
ばかシでなく身分証明書等多様な用途に使用することが
考えられている。This IC card has a larger storage capacity and better security than the magnetic stripe cards that are already widely used, so it can be used for a variety of purposes such as identification cards, rather than the traditional magnetic stripe cards. It is considered to be used for this purpose.
ICカードは、塩化ビニル等のプラスチックカードに、
リーダー・ライター等の外部装置との接続用端子を有す
る集積回路装置が搭載された構成であり、この集積回路
装置は極めて薄型にするこ゛とが必要とされる。このた
め、従来の集積回路装置は、第3図に断面を示すように
、フィルム上の絶縁基板31に外部接続用端子パターン
322回路パターン33およびスルーホール34等の配
線導体を形成した薄型配線基板に、集積回路素子36を
ダイスポンディングし、集積回路素子36の入出力電極
と回路パターン33とをワイヤーボンディング方式等に
よシ金属線36で接続する。また樹脂封止時の樹脂なか
れ止め用の封止枠37を配線基板に接着して設け、エポ
キシ樹脂等の封止樹脂38によ)封止している。(特開
昭55−56647号公報、特開昭58−92597号
公報)発明が解決しようとする課題
ICカードに搭載されている集積回路装置は、薄型化と
同時に、高信頼性、高寸法精度、さらに低コストである
ことが求められている。しかしながら、前述したような
集積回路装置においては、次のような問題点を有してい
る。(1)配線基板が高価である。(2)スルーホール
34の形成はめっきによシ行うのでスルーホール形成時
のめっき厚さのばらつきが配線基板の総厚のばらつきと
なり、良好な厚さ精度が得にくい。(3)集積回路素子
36の樹脂封止時に、封止樹脂38がスルーホール34
より流出するので、流出防止のためスルーホール34を
封口する手段が必要である。IC cards are plastic cards made of vinyl chloride, etc.
It has a configuration in which an integrated circuit device having a terminal for connection with an external device such as a reader/writer is mounted, and this integrated circuit device needs to be made extremely thin. For this reason, the conventional integrated circuit device is a thin wiring board in which wiring conductors such as an external connection terminal pattern 322, a circuit pattern 33, and a through hole 34 are formed on an insulating substrate 31 on a film, as shown in cross section in FIG. Next, the integrated circuit element 36 is die-bonded, and the input/output electrodes of the integrated circuit element 36 and the circuit pattern 33 are connected with metal wires 36 by wire bonding or the like. Further, a sealing frame 37 for preventing resin leakage during resin sealing is provided by adhering to the wiring board, and the wiring board is sealed with a sealing resin 38 such as epoxy resin. (Japanese Unexamined Patent Publications No. 55-56647, No. 58-92597) Problems to be Solved by the Invention The integrated circuit devices mounted on IC cards are thinner, have high reliability, and have high dimensional accuracy. , there is a need for even lower costs. However, the above-described integrated circuit device has the following problems. (1) The wiring board is expensive. (2) Since the through-holes 34 are formed by plating, variations in the plating thickness during the formation of the through-holes result in variations in the total thickness of the wiring board, making it difficult to obtain good thickness accuracy. (3) When the integrated circuit element 36 is sealed with resin, the sealing resin 38 is inserted into the through hole 34.
Therefore, a means for sealing the through hole 34 is required to prevent leakage.
一方、所望する形状に加工されたリードフレームを用い
、その片面を外部接続用端子、他面を集積回路素子搭載
接続面とし、リードフレームの外部接続用端子を除く部
分と集積回路素子とを封止樹脂で覆った集積回路装置は
、上記のような高精度な精密配線基板を必要としないの
で高寸法精度でかつ高効率に製造でき、しかも安価であ
るという長所があるが、外形寸法からの制約があり、製
造上多くの困難な点を残している。たとえば、ICカー
ドの厚さは、l5O(国際標準化機構)規格により76
0±80μmと定められておυ、また集積回路装置搭載
により生ずる工Cカード表面の凹凸は、カードの機械的
強度や磁気ストライプ読み誤り防止の観点から小さく抑
えられなければいけないが、集積回路装置のたわみが大
きい場合には、カードに搭載した際に上記の寸法を満足
することが困難となるほか、たわみによって生ずるスト
レスのために集積回路素子が破損するといった問題点を
有している。On the other hand, a lead frame processed into a desired shape is used, one side of which is used as an external connection terminal, and the other side used as a connection surface for mounting an integrated circuit element, and the part of the lead frame other than the external connection terminal is sealed with the integrated circuit element. Integrated circuit devices covered with adhesive resin do not require the above-mentioned high-precision precision wiring boards, so they can be manufactured with high dimensional accuracy and high efficiency, and have the advantage of being inexpensive. There are limitations and many manufacturing difficulties remain. For example, the thickness of an IC card is 76 mm according to the 15O (International Organization for Standardization) standard.
0 ± 80 μm, and the unevenness on the surface of the C card caused by mounting an integrated circuit device must be kept small from the viewpoint of the card's mechanical strength and prevention of misreading of the magnetic stripe. If the deflection is large, it becomes difficult to satisfy the above-mentioned dimensions when mounted on a card, and the integrated circuit element may be damaged due to the stress caused by the deflection.
本発明は、このような問題点を解決するもので、リード
フレームを用いて集積回路装置を構成し、そのたわみを
一定値以下に抑えることを目的とするものである。The present invention is intended to solve these problems, and aims to construct an integrated circuit device using a lead frame, and to suppress the deflection thereof to a certain value or less.
課題を解決するための手段
この問題点を解決するために本発明は、リードフレーム
の片方の少なくとも一部を外部接続用端子とし、他方の
而に集積回路素子を搭載接続し、mI記リードフレーム
の他方の面の集積回路素子を少なくとも封止樹脂で覆う
とともに、この封止樹脂と前記リードフレームの線膨張
係数の差を、7X 1o−6/’c以下とするものであ
る。Means for Solving the Problems In order to solve this problem, the present invention provides an mI lead frame in which at least a part of one side of the lead frame is used as a terminal for external connection, and an integrated circuit element is mounted and connected to the other side. The integrated circuit element on the other side of the lead frame is covered with at least a sealing resin, and the difference in coefficient of linear expansion between the sealing resin and the lead frame is set to 7X 1o-6/'c or less.
布団
本発明は上記した構成によって、従来用いられていた高
密度な精密回路基板を必要とせず、安価で隠めて一般的
なリードフレームが使用でき、しかも集積回路装置とし
ての厚みが容易に製造できるとともに、たわみを一定値
以下に押えることが可能となる。Due to the above-described structure, the present invention does not require the high-density precision circuit board used in the past, allows the use of a general lead frame that is inexpensive and hidden, and can be easily manufactured to a thickness as an integrated circuit device. At the same time, it becomes possible to suppress the deflection below a certain value.
実施例
以下、本発明の一実施例の集積回路装置について図面を
謬照しながら説明する。、第1図は本発明の実施例にお
ける構成の集積回路装置の断面を示すものである。Embodiment Hereinafter, an integrated circuit device according to an embodiment of the present invention will be described with reference to the drawings. , FIG. 1 shows a cross section of an integrated circuit device configured in an embodiment of the present invention.
第1図のごとく本実施例においては、帯状の金属性素材
からフォトエツチング加工等により所定の形状に形成さ
れたリードフレーム40に、金等のめっきを施して片方
の面を外部接続用端子402Lとし、他方の而40bに
集積回路素子5oをダイスボンドし、金、アルミ、銅等
の材質のワイヤーボンディング6oにより他方の而40
bと集積回路素子6oの接続パッド部とを接続している
。この部分はワイヤーを使用しないフェイスボンディン
グあるいはテープキャリアで実施することもできる。集
積回路素子50とリードフレーム40との必要な接続を
行った後、エポキシ等の成形材料を用いてトランスファ
成形法で封止樹脂70により集積回路素子5oを覆い、
保護する。このことにより集積回路装置100が得られ
る。As shown in FIG. 1, in this embodiment, a lead frame 40 is formed from a band-shaped metallic material into a predetermined shape by photo-etching or the like, and is plated with gold or the like, and one side is provided with an external connection terminal 402L. Then, the integrated circuit element 5o is die-bonded to the other part 40b, and the other part 40 is bonded to the other part 40 by wire bonding 6o made of material such as gold, aluminum, copper, etc.
b and the connection pad portion of the integrated circuit element 6o are connected. This part can also be implemented with wireless face bonding or with a tape carrier. After making the necessary connections between the integrated circuit element 50 and the lead frame 40, the integrated circuit element 5o is covered with a sealing resin 70 by a transfer molding method using a molding material such as epoxy.
Protect. As a result, an integrated circuit device 100 is obtained.
このトランスファ成形法についてさらにくわしく説明す
る。まず、集積回路素子60を実装したリードフレーム
4oを温度170〜180’Cに設定されたトランスフ
ァ成形機の金型にセツティングし、次に70〜90’C
に予備加熱されたエポキン成形樹脂をトランスファチャ
ンバー内に挿入し、加熱加圧のもとにあらかじめ密封さ
れたキャビティ内にこれを射出させて硬化する。このと
きの成形条件は、成形温度=170〜180’C,成形
圧カニ 3o 〜1ookq/cri 、 成形時間
= 40〜120SeCである。This transfer molding method will be explained in more detail. First, the lead frame 4o on which the integrated circuit element 60 is mounted is set in a mold of a transfer molding machine set at a temperature of 170 to 180'C, and then heated to a temperature of 70 to 90'C.
The preheated Epokin molding resin is inserted into the transfer chamber, and is injected into the pre-sealed cavity under heat and pressure to harden. The molding conditions at this time are molding temperature = 170 to 180'C, molding pressure 3 o to 1ookq/cri, and molding time = 40 to 120 SeC.
以上のように構成された集積回路装置100について、
リードフレーム材及び封止樹脂材を種々に変化させた場
合のたわみを以下に説明する。Regarding the integrated circuit device 100 configured as above,
Deflection when the lead frame material and the sealing resin material are variously changed will be explained below.
〈第1表〉は、本実施例において用いたリードフレーム
材及び封止樹脂材の線膨張係数である。Table 1 shows the linear expansion coefficients of the lead frame material and sealing resin material used in this example.
く第1表〉 リードフレーム材及び封止樹脂材の線膨張
係数
〈第2表〉はリードフレーム材と封止樹脂材を種々組み
合せて作製した集積回路装置の外部接続用端子面におけ
るたわみである。ただしリードフレームの厚さは150
μm、封止樹脂層の厚さは4BOfimであり、たわみ
は集積回路装置の対角12.6羽における値である。Table 1: Linear expansion coefficients of lead frame materials and sealing resin materials (Table 2) is the deflection at the external connection terminal surface of integrated circuit devices fabricated by various combinations of lead frame materials and sealing resin materials. . However, the thickness of the lead frame is 150
The thickness of the sealing resin layer is 4BOfim, and the deflection is the value at 12.6 diagonals of the integrated circuit device.
〈第2表〉 各組み合せにおける集積回路装置のたわみ
第2図は、線膨張係数の差とたわみの関係をグラフに示
したものである。同図より、線膨張係数の差が小さい組
み合せほど集積回路装置のたわみが小さいことがわかる
。<Table 2> Deflection of the integrated circuit device in each combination FIG. 2 is a graph showing the relationship between the difference in linear expansion coefficient and the deflection. From the figure, it can be seen that the smaller the difference in linear expansion coefficients between the combinations, the smaller the deflection of the integrated circuit device.
次に、集積回路装置のたわみと機械的強度の関係を示す
。〈第3表〉は、集積回路装置をカードに搭載し、繰り
返しローラー通過試験を行った結果である。Next, the relationship between deflection and mechanical strength of an integrated circuit device will be shown. Table 3 shows the results of repeated roller passing tests with integrated circuit devices mounted on cards.
〈第3表〉 ローラー通過試験結果
以上より、2okqf’のローラー通過試験に耐えるた
めには、たわみを50μm以下に抑えなければならない
ことがわかる。そして第2図より、集積回路装置のたわ
みを50μm以下とするためにはリードフレーム4oと
封止樹脂Toの線膨張係数の差を7X10/”C以下と
しなければならない。<Table 3> Roller passing test results From the above, it can be seen that in order to withstand the roller passing test of 2okqf', the deflection must be suppressed to 50 μm or less. From FIG. 2, in order to keep the deflection of the integrated circuit device to 50 μm or less, the difference in linear expansion coefficient between the lead frame 4o and the sealing resin To must be 7×10/”C or less.
以上のように本実施例によれば、リードフレーム40と
封止樹脂700線膨張係数の差を7×10−6/°C以
下となるように組み合せることにより、集積回路のたわ
みを50μm以下に抑え、寸法精度及び機械的強度を向
上させることができる。As described above, according to this embodiment, by combining the lead frame 40 and the sealing resin 700 so that the difference in linear expansion coefficient is 7×10-6/°C or less, the deflection of the integrated circuit can be reduced to 50 μm or less. dimensional accuracy and mechanical strength can be improved.
発明の効果
以上のように本発明は、リードフレームの片方の面の少
なぐとも一部を外部接続用端子とし、他方の面に集積回
路素子を搭載接続し、前記リードフレームの他方の面の
集積回路素子を少なくとも封止樹脂で覆った構成におい
て、この封止樹脂と@記す−ドフレームの線膨張係数の
差を7×10−6/°C以下となるように組み合せるこ
とにより、高精度な精密回路基板を必要とせず、安価で
極めて一般的なリードフレームが使用でき、しかも製造
時に生ずるたわみを小さくして寸法精度及び機械的強度
を向上させ、ICカード搭載用集積回路装置としての実
用性ならびに信頼性を高めることができる。Effects of the Invention As described above, in the present invention, at least a part of one side of a lead frame is used as an external connection terminal, an integrated circuit element is mounted and connected on the other side, and the other side of the lead frame is connected to the external connection terminal. In a structure in which an integrated circuit element is covered with at least a sealing resin, high efficiency can be achieved by combining the sealing resin and the frame so that the difference in linear expansion coefficient is 7×10-6/°C or less. It does not require a high-precision precision circuit board and can use an inexpensive and extremely common lead frame.Moreover, it reduces the deflection that occurs during manufacturing and improves dimensional accuracy and mechanical strength, making it suitable for use as an integrated circuit device for mounting IC cards. Practicality and reliability can be improved.
第1図は本発明の一実施例における集積回路装置の断面
図、第2図は集積回路装置のたわみと線膨張係数の差の
関係についての検討結果を示す説明図、第3図は従来の
集積回路装置の断面図である。
4o・・・・・・リードフレーム、40a・・・・・・
リードフレームの片方の而、40b・・・・・・リード
フレームの他方の面、6o・・・・・・集積回路素子、
60・・・・・ワイヤーボンディング、70・・・・・
・封止樹脂、1oO・・・・・・集積回路装置。
代理人の氏名 弁理士 粟 野 重 孝 ほか1名図
末芙月乞S従不采イタの差
CttO−’/”c−)
蜀−−−ワードフシ−へ
lθθ−M=櫂固蒐衷1FIG. 1 is a cross-sectional view of an integrated circuit device according to an embodiment of the present invention, FIG. 2 is an explanatory diagram showing the results of an investigation on the relationship between the deflection of the integrated circuit device and the difference in linear expansion coefficient, and FIG. 1 is a cross-sectional view of an integrated circuit device. 4o...Lead frame, 40a...
One side of the lead frame, 40b... The other side of the lead frame, 6o... Integrated circuit element,
60...Wire bonding, 70...
- Sealing resin, 1oO...Integrated circuit device. Name of agent: Patent attorney Shigetaka Awano and one other person
Claims (1)
用端子とし、他方の面に集積回路素子を搭載接続し、前
記リードフレームの他方の面の集積回路素子を少なくと
も封止樹脂で覆い、上記封止樹脂と前記リードフレーム
の線膨張係数の差を7×10^−^6/℃以下とした集
積回路装置。At least a part of one side of the lead frame is used as an external connection terminal, an integrated circuit element is mounted and connected on the other side, the integrated circuit element on the other side of the lead frame is covered with at least a sealing resin, and the above-mentioned sealing is performed. An integrated circuit device in which the difference in coefficient of linear expansion between the adhesive resin and the lead frame is 7×10^-^6/°C or less.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63187224A JPH0236552A (en) | 1988-07-27 | 1988-07-27 | Integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63187224A JPH0236552A (en) | 1988-07-27 | 1988-07-27 | Integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0236552A true JPH0236552A (en) | 1990-02-06 |
Family
ID=16202240
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63187224A Pending JPH0236552A (en) | 1988-07-27 | 1988-07-27 | Integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0236552A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04196568A (en) * | 1990-11-28 | 1992-07-16 | Mitsubishi Electric Corp | Resin-sealed semiconductor device |
-
1988
- 1988-07-27 JP JP63187224A patent/JPH0236552A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04196568A (en) * | 1990-11-28 | 1992-07-16 | Mitsubishi Electric Corp | Resin-sealed semiconductor device |
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