JPH0237697B2 - - Google Patents

Info

Publication number
JPH0237697B2
JPH0237697B2 JP58074542A JP7454283A JPH0237697B2 JP H0237697 B2 JPH0237697 B2 JP H0237697B2 JP 58074542 A JP58074542 A JP 58074542A JP 7454283 A JP7454283 A JP 7454283A JP H0237697 B2 JPH0237697 B2 JP H0237697B2
Authority
JP
Japan
Prior art keywords
weir
protective layer
resin
ink
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58074542A
Other languages
Japanese (ja)
Other versions
JPS59200426A (en
Inventor
Toshio Yoshihara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nidec Precision Corp
Original Assignee
Nidec Copal Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nidec Copal Corp filed Critical Nidec Copal Corp
Priority to JP58074542A priority Critical patent/JPS59200426A/en
Publication of JPS59200426A publication Critical patent/JPS59200426A/en
Publication of JPH0237697B2 publication Critical patent/JPH0237697B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To obtain the arbitrary and minute complicate form of a protective layer in response to a circuit by printing and forming a pattern of a weir by using prining ink into which expandable particulates are mixed, injecting a resin to a section surrounded by the weir and shaping the protective layer. CONSTITUTION:A pattern 10 afterwards functioning as a weir is printed and formed on a substrate 1, to which wirings 3 are wired, through a screen printing method by using expandable printing ink, and an IC chip 2 is die-bonded similarly on the substrate 1 with adhesives 7. When the substrate to which the weir pattern is printed and formed is heated and treated, printed expandable ink foams and expands, height increases, and 10a is shaped. Adhesives 7 bonding the IC chip 2 cure simultaneously. The IC chip 2 and the wirings 3 on the substrate are connected 4 through wire bonding. A resin for shaping a protective layer 5 is injected to the weir 10a formed by the foaming and expansion of expandable ink, and the weir section is sealed completely.

Description

【発明の詳細な説明】 本発明は、樹脂等を用いて微細物の部分的保護
層を形成する場合、微細物が一箇所あるいは複数
個所であつても封止樹脂の流出防止の堰を同時に
精度よく形成でき、且つ堰パターンの形状を任意
に設定可能とした部分的封止方法に関する。
DETAILED DESCRIPTION OF THE INVENTION When a partial protective layer for fine particles is formed using a resin or the like, the present invention can simultaneously create a weir to prevent the sealing resin from flowing out even if the fine particles are in one place or in multiple places. The present invention relates to a partial sealing method that allows formation with high accuracy and allows the shape of a weir pattern to be arbitrarily set.

従来、たとえばセラミツクあるいは樹脂等の配
線基板上に混成集積回路を形成する際に、搭載さ
れたICチツプ等と基板上の配線部との間をワイ
ヤボンデイング等の方法により結線部、該結線
部、もしくは該結線部にICチツプをも含めて部
分的に樹脂等により保護層を設けている。この保
護層形成の樹脂は、加熱処理(通常120℃〜150℃
程度)して硬化させている。しかし、結線ワイ
ヤ、ICチツプそして基板と各々の熱膨張係数が
異なるため、常温に戻る際に各々の界面において
応力が働いて、結線ワイヤの断線等のトラブルが
発生する怖れがあつた。これを防止するためには
応力を小さくしてやればよく、その方法としては
保護樹脂層の熱膨張係数あるいは弾性率を変える
等が考えられるが、通常は樹脂の使用量をできる
だけ少なくしつつ、且つ保護する部分も最小限に
する部分的封止方法が用いられている。
Conventionally, when forming a hybrid integrated circuit on a wiring board made of ceramic or resin, for example, a method such as wire bonding is used to connect a mounted IC chip, etc. and a wiring part on the board. Alternatively, a protective layer made of resin or the like is provided partially on the connection portion, including the IC chip. The resin used to form this protective layer is heat treated (usually at 120°C to 150°C).
degree) and harden it. However, since the thermal expansion coefficients of the connecting wires, IC chips, and substrates are different, there is a risk that stress will be applied at each interface when the temperature returns to room temperature, causing problems such as disconnection of the connecting wires. In order to prevent this, the stress can be reduced, and one possible way to do this is to change the thermal expansion coefficient or elastic modulus of the protective resin layer, but usually the amount of resin used is as small as possible, and the protective A partial sealing method is used to minimize the amount of parts that are exposed.

たとえば第1図に示す従来例では、基板1の上
に配線3を施し、ICチツプ2を接着剤7により
固定し、ワイヤボインデイングにより結線4を設
け、樹脂を注入して保護層5を形成したものであ
るが、樹脂の流出を防止する手段を何等施してい
ない為、不必要な部分へも樹脂が流出してしま
い、結果的に樹脂の使用量を減らすまでに至らな
い。樹脂の流出を防止するために第2図に示すよ
うに、保護する部分の周囲に、フエノール樹脂等
を用いて成形された枠6を接着剤にて接着して、
これを樹脂流出を防ぐ堰としようとした方法があ
る。
For example, in the conventional example shown in FIG. 1, wiring 3 is provided on a substrate 1, an IC chip 2 is fixed with an adhesive 7, connections 4 are provided by wire bonding, and a protective layer 5 is formed by injecting resin. However, since no means were taken to prevent the resin from flowing out, the resin would leak into unnecessary areas, and as a result, the amount of resin used could not be reduced. In order to prevent the resin from flowing out, a frame 6 made of phenol resin or the like is glued around the area to be protected, as shown in FIG.
There is a method to use this as a dam to prevent resin from flowing out.

この方法により樹脂の使用量は減少したが、枠
を成形し、さらに接着し固定するという工程を増
加させた。一方、枠6は基板1に密着させる必要
があるために反り、ネジレ等の無い平面性を要求
されつつ、接着面積をある程度必要としながら
も、基板上では幅を狭くすることを要求され、さ
らに基板1の配線に応じて細かく且つ複雑な形状
を要求されながらも任意に設定することは非常に
困難であつた。
This method reduced the amount of resin used, but increased the steps of molding the frame and gluing and fixing it. On the other hand, since the frame 6 needs to be in close contact with the substrate 1, it is required to have flatness without warping or twisting, and although it requires a certain amount of adhesive area, it is also required to have a narrow width on the substrate. Although a fine and complicated shape is required depending on the wiring of the substrate 1, it is extremely difficult to set the shape arbitrarily.

本発明は、上述のように従来例に見られた不都
合に鑑み、混成集積回路の製造工程を簡素化しつ
つ、保護層の形成に有用な堰を設けるために、発
泡性印刷用インク、たとえば発泡性微粒子(商品
各エクスパンセル:日本フイライト製等)を混入
させた印刷用インクを用いて、保護層を設ける必
要のある一箇所あるいは複数箇所に対して、堰の
パターンをスクリーン印刷法にて同時に印刷形成
し、該パターン印刷形成後に加熱して該発泡性イ
ンクの発泡膨張を促し、該膨張により少なくとも
樹脂の流出を防ぐ高さを有する堰と成し、該堰に
より包囲された部分へ樹脂を注入して硬化させる
ことによつて保護層を形成し、且つ堰パターンの
形状を任意に設定可能としたことを特徴とした部
分的封止方法を提供するものである。
In view of the disadvantages seen in the prior art as described above, the present invention provides a foam printing ink, for example, a foam printing ink, in order to simplify the manufacturing process of hybrid integrated circuits and provide a weir useful for forming a protective layer. A weir pattern is screen printed on one or more locations where a protective layer needs to be provided, using printing ink mixed with sexual fine particles (Each Expancel product: manufactured by Nippon Fluite, etc.). At the same time, the pattern is printed, and after the pattern is printed, it is heated to promote foaming and expansion of the foamable ink, and the expansion forms a weir having a height that prevents at least the resin from flowing out, and the resin is applied to the area surrounded by the weir. The present invention provides a partial sealing method characterized in that a protective layer is formed by injecting and curing a weir pattern, and the shape of a weir pattern can be arbitrarily set.

第3図は本発明の実施例で、形成順序の第1番
目を示す図。配線3を施された基板1の上に、発
泡性印刷用インクを用いてスクリーン印刷法によ
り後に堰と成るパターン10を印刷形成してや
り、ICチツプ2を同じく基板1の上に接着剤7
にてダイボンデイングを終えた状態を示してい
る。
FIG. 3 is an embodiment of the present invention, and is a diagram showing the first formation order. On the substrate 1 on which the wiring 3 has been applied, a pattern 10 that will later become a dam is printed by screen printing using foam printing ink, and the IC chip 2 is also placed on the substrate 1 with an adhesive 7.
This shows the state after die bonding.

第4図は本発明の実施例で、形成順序の第2番
目を示す図。第3図において堰パターンを印刷形
成された基板を加熱処理してやると、印刷されて
いる発泡性インクが発泡膨張し、高さが増大して
堰10aを形成する。また同時に、ICチツプ2
を接着している接着剤7が硬化する。さらに、
ICチツプ2と基板上の配線3との間を、ワイヤ
ボンデイングにより結線4を施した状態を示して
いる。
FIG. 4 is an embodiment of the present invention, and is a diagram showing the second formation order. In FIG. 3, when the substrate on which the weir pattern is printed is heat-treated, the printed foaming ink expands and increases in height to form the weir 10a. At the same time, IC chip 2
The adhesive 7 that adheres them is cured. moreover,
A state in which a connection 4 is made between an IC chip 2 and a wiring 3 on a substrate by wire bonding is shown.

第5図は本発明の実施例で、形成順序の第3番
目で最終段階を示す図。発泡性インクの発泡膨張
により形成された堰10aに、保護層形成のため
の樹脂を注入して、当該部分の封止を終了した状
態を示している。
FIG. 5 is a diagram showing the third and final stage of the formation sequence in an embodiment of the present invention. The figure shows a state in which a resin for forming a protective layer is injected into the weir 10a formed by the expansion of the foaming ink, and the sealing of the part is completed.

本実施例では、加熱発泡性微小粒子をインクに
混入させたものを発泡性印刷用インクとして用い
るが、インクに発泡剤(加熱により分解して気体
を発生する無機もしくは有機化合物であつて、一
般に分解性発泡剤と呼ばれるもの。あるいは、常
温中では気体もしくは揮発生液体であるところの
一般に揮発生発泡剤と呼ばれるもの)を混入した
ものであつても、あるいは乾燥、硬化反応時にガ
スを発生した発泡するインクを用いるものであつ
ても構わないものである。また、本実施例にあつ
ては加熱による熱処理を施すことにより発泡膨張
を促しているが、自然放置にて発泡膨張するもの
であつてもよいし、また冷却、加減圧、あるいは
電子線、紫外線等を照射することで反応発泡する
ものであつても構わない。
In this example, ink mixed with heat-expandable microparticles is used as a foamable printing ink. Even if it contains a decomposable blowing agent (or a volatile blowing agent that is a gas or volatile liquid at room temperature), or one that generates gas during drying or curing reactions. It is also possible to use ink that foams. In addition, in this example, foaming and expansion is promoted by applying heat treatment by heating, but foaming and expanding may be allowed to occur naturally, or by cooling, pressurization, electron beams, ultraviolet rays, etc. It is also possible to use a material that reacts and foams by irradiating it.

印刷方法についても、本実施例中ではスクリー
ン印刷法を用いているが、同等の効果が得られる
他の印刷方法を用いてもよい。
Regarding the printing method, although a screen printing method is used in this embodiment, other printing methods that can obtain the same effect may be used.

またワイヤボンデイングによる結線前に発泡膨
張させているが、ボンデイングおよび印刷に支障
がなければ結線後にインクの発泡膨張を行わせる
ものであつても構わない。
Although the ink is foamed and expanded before wire bonding, the ink may be foamed and expanded after wire bonding as long as it does not interfere with bonding and printing.

さらに、本実施例では混成集積回路の製造工程
におけるICチツプの樹脂保護層による封止につ
いて述べているが、たとえば抵抗体等の他の電子
部品の封止に用いてもよく、機械加工工程にあつ
て、例えばネジの封止あるいは接着剤の流出防止
等に応用できるものであることはもちろんのこと
である。
Furthermore, although this example describes the encapsulation of an IC chip with a resin protective layer in the manufacturing process of a hybrid integrated circuit, it may also be used to encapsulate other electronic components such as resistors, and may be used in the machining process. Of course, it can be applied to, for example, sealing screws or preventing adhesive from flowing out.

以上本発明を用いることにより、堰とする成形
品の加工精度にとらわれることなく、回路に応じ
た保護層の形状を任意に、且つ成型品による堰形
成に比して微細で複雑な形状を得ることが可能と
なり、さらに数箇所に堰を設ける場合において
も、数箇所のパターンを同時に形成することが可
能となる。
As described above, by using the present invention, the shape of the protective layer can be arbitrarily set according to the circuit without being limited by the processing accuracy of the molded product used as a weir, and a finer and more complex shape can be obtained compared to the weir formation using a molded product. Furthermore, even when weirs are provided at several locations, patterns at several locations can be formed at the same time.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来例で、流出防止の堰を用いていな
い状態の基板の断面図で、第2図は従来例のう
ち、別成形の枠を接着して堰を設けるようにした
基板の断面図で、第3図は本発明の実施例で、形
成順序の第1番目の基板断面図で、第4図は同じ
く第2番目を示す基板断面図で、第5図は同じく
第3番目を示す断面図で、第6図は本発明を用い
た混成集積回路の斜視略図である。 1……基板、2……ICチツプ、3……配線、
4……結線、5……保護層、6……枠、7……接
着剤、10……堰パターン(膨張前の状態)、1
0a……堰パターン(膨張後の状態)。
Figure 1 is a cross-sectional view of a conventional board without a weir to prevent leakage, and Figure 2 is a cross-sectional view of a conventional board with a weir provided by gluing a separately molded frame. In the figures, FIG. 3 is a sectional view of the first substrate in the embodiment of the present invention, FIG. 4 is a sectional view of the second substrate, and FIG. 5 is a sectional view of the third substrate. FIG. 6 is a schematic perspective view of a hybrid integrated circuit using the present invention. 1... Board, 2... IC chip, 3... Wiring,
4... Connection, 5... Protective layer, 6... Frame, 7... Adhesive, 10... Weir pattern (state before expansion), 1
0a...Weir pattern (state after expansion).

Claims (1)

【特許請求の範囲】 1 混成集積回路等の実装工程にあつて、樹脂等
を用いて部分的保護層を形成し、微細部を封止す
る場合において、 回路基板上に、加熱することで膨張する発泡性
インクを用いて、スクリーン印刷法で樹脂の流出
を防止する堰のパターンを一箇所もしくは複数の
必要部分に印刷形成し、該パターンを印刷形成後
に加熱することにより、印刷された前記発泡性イ
ンクを発泡膨張させ、該膨張により少なくとも樹
脂の流出を防ぐ高さを有する堰と成し、該堰によ
つて包囲された部分へ樹脂等を注入硬化させて保
護層と成すことを特徴とする部分的封止方法。
[Scope of Claims] 1. In the mounting process of hybrid integrated circuits, etc., when a partial protective layer is formed using resin etc. to seal minute parts, on a circuit board, when heated, it expands. Using a foaming ink, a weir pattern for preventing resin outflow is printed on one or more necessary parts using a screen printing method, and the pattern is heated after printing to form the printed foam. The protective layer is formed by foaming and expanding the adhesive ink, forming a weir having a height that prevents at least resin from flowing out by the expansion, and injecting and hardening resin etc. into the area surrounded by the weir to form a protective layer. partial sealing method.
JP58074542A 1983-04-27 1983-04-27 Partial sealing method Granted JPS59200426A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58074542A JPS59200426A (en) 1983-04-27 1983-04-27 Partial sealing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58074542A JPS59200426A (en) 1983-04-27 1983-04-27 Partial sealing method

Publications (2)

Publication Number Publication Date
JPS59200426A JPS59200426A (en) 1984-11-13
JPH0237697B2 true JPH0237697B2 (en) 1990-08-27

Family

ID=13550252

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58074542A Granted JPS59200426A (en) 1983-04-27 1983-04-27 Partial sealing method

Country Status (1)

Country Link
JP (1) JPS59200426A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2590811B2 (en) * 1986-01-09 1997-03-12 ソニー株式会社 Electric circuit device
JPH02296373A (en) * 1989-05-10 1990-12-06 Mitsubishi Electric Corp Semiconductor device

Also Published As

Publication number Publication date
JPS59200426A (en) 1984-11-13

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