JPH0237809A - oscillation circuit - Google Patents

Abstract

PURPOSE:To obtain a miniature oscillating circuit of low power consumption by providing a third insulated gate type field effect transistor connected in series to a complementary pair insulated gate type field effect transistor and setting high the ON resistance of this transistor. CONSTITUTION:In addition to a pair of P-MOSTr(P-channel type MOS transistor) 3 and an N-MOSTr(N-channel type MOS transistor) 4, an N-MOSTr 7 is connected in series between a negative-side power source terminal VSS and the source side of the N-MOSTr 4 as the third transistor. Further, in order to control its gate voltage, a P-MOSTr 8 as a fourth transistor and a resistance are connected in series to constitute a low voltage source and its middle point voltage VN is supplied to the gate electrode of the N-MOSTr 7. The ON resistance of the gate voltage of the N-MOSTr 7 is set high. Thus, a through current IO is limited by the N-MOSTr 7 and the total power consumption is decreased remarkably.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an oscillation circuit coupled with a solid-state resonator.

Conventional technologyAn oscillation circuit that combines an inverter circuit (hereinafter referred to as a CMOS inverter) using a complementary pair of insulated gate field effect transistors and a crystal resonator has a stable oscillation period, and is suitable for digital watches such as clocks and watches. ,micro·
It is used as a reference clock signal generation source in the field of processors.

FIG. 1 shows a conventional standard oscillation circuit, including a crystal resonator 1, a feedback resistor 2, a P-channel MOS transistor (hereinafter abbreviated as P-MO3Tr) 3, and an N-channel MOS transistor (hereinafter referred to as N- A stable and unique oscillation output can be obtained by applying a predetermined voltage between the power supply terminals VDD and VSS.

Problems to be Solved by the Invention However, in this conventional oscillation circuit, in order to ensure stable oscillation ability, P-MO3Tr3 and N-MO3
For both Tr4, the ratio of the channel width W to the channel length, that is, the W/L value is set to be large. For example, the W/L value is 10 to 2 compared to the transistor of a normal CMOS logic circuit.
About 0 times larger. In this case, it is an important issue to reduce the through current Io of the oscillation circuit.

The present invention achieves low current in an oscillation circuit having a CMOS inverter configuration, and also provides an oscillation circuit that is optimal for integration into an integrated circuit.

Means for Solving the Problems The present invention provides a CMOS with a resonator coupled between input and output terminals.
This is an oscillation circuit in which a third MOS transistor is connected in series in an inverter configuration, and the gate potential of the third MOS transistor is maintained at a conduction potential of the third MOS transistor near the threshold value.

Effect: As a result, the current consumed by the CMOS inverter of the oscillation circuit, so-called inverter through current, can be reduced.

Embodiment FIG. 1 is a circuit diagram of an oscillation circuit according to an embodiment of the present invention.
A pair of P-MO8Tr3 and N- in the OS inverter configuration
In addition to MO3Tr4, as a third transistor, N-
MO8Tr7 is connected to power supply terminal vSS and N-MO8Tr4
P-MO8 is connected in series with the source side of the P-MO8 as a fourth transistor to control its gate voltage.
The transistor 8 and the resistor 9 are connected in series to constitute a low voltage source, and the midpoint potential VN thereof is supplied to the gate electrode of the N-MO5Tr7.

In the circuit configuration of this example, N-MO8Tr7 is CMO
To limit the through current 10 when the S inverter circuit is in a transient state. That is, the current characteristics of an insulated gate field effect transistor satisfy the following relationship.

103=β(Vas-Vr)2 Here, fos is the drain-source current, VaS is the gate-source voltage, vr is the threshold voltage, and β is a constant determined by the process and design. As can be seen from this relational expression, if the gate-source voltage Vas (hereinafter simply referred to as gate voltage) of the N-MO8Tr7 is reduced (and set near the threshold voltage Vr), the N-M
The current in O3Tr7 is significantly reduced. P- in Figure 1
The series circuit configuration of MO8Tr8 and resistor 9 is a gate voltage supply source of N-MOSTr7 connected in series to the CMOS inverter circuit. Thereby, the gate voltage of the N-MO3Tr7 can be set stably and practically low, and the on-resistance can be increased.

The P-MO8Tr3 and N-MO3Tr4 constituting the CMOS inverter circuit have a relatively large W/L value so as to have stable oscillation ability. This also limits the through current 10 by the N-MO8Tr7, and the total power consumption is significantly reduced.

Effects of the Invention According to the present invention, a third insulated gate field effect transistor is provided, connected in series to a complementary pair of insulated gate field effect transistors of a CMOS inverter circuit configuration coupled to an image pickup element, and a third insulated gate field effect transistor is provided. By setting the on-resistance high, the through current of the CMOS inverter circuit is limited, and a small oscillation circuit with small current consumption and low power consumption can be realized. This allows electronic devices that use battery power to
This is effective in extending the life of the battery.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an oscillation circuit according to an embodiment of the present invention, and FIG.
FIG. 2 is a circuit diagram of a conventional example. 1...Crystal oscillator, 2...Feedback resistor,
3, 8...P-MO8Tr, 4, 7-...-
・N-MOS Tr, 5.6... Capacitor, 9... Resistor for gate voltage control.

Claims (1)

[Claims] A third MOS transistor is connected in series to a CMOS inverter configuration in which a resonator is coupled between the input and output terminals,
An oscillation circuit that maintains the gate potential of this transistor at the same transistor conduction potential near the threshold.