JPH023877A - Single-chip microcomputer - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to an improvement in the interrupt function of a single-chip microcomputer.

(b) Conventional technology Advances in semiconductor manufacturing technology have enabled arithmetic and logic units,
It has become possible to form not only an accumulator, but also a memory and various interfaces on one silicon chip. This type of microcomputer is called a single-chip microcomputer, and initially it was mostly oriented toward application purposes, but today it has processor functions comparable to general-purpose microcomputers, expandability, and versatile interface functions. We are prepared.

Therefore, multiprocessor systems using such high-performance, highly functional single-chip microcomputers are beginning to be considered.

Now, in a multiprocessor system, each processor is rarely able to operate independently, and often continues to operate while exchanging data with each other, but one processor's data generation or data request is received from another processor. Since this occurs randomly, an interrupt function is used for data communication between processors.

For this reason, multiprocessor systems using general-purpose microcomputers use dedicated interrupt controllers or interrupts via external interrupt input, but in multiprocessor systems using single-chip microcomputers, dedicated interrupt controllers are In many cases, this is not possible due to the difference in performance, and the use of a dedicated interrupt controller has the disadvantage that a good interrupt/performance ratio cannot be obtained. Furthermore, interrupts caused by external interrupt inputs have the disadvantage that single-chip microcomputers cannot handle many causes of interrupts due to limitations on the number of pins and other factors, and the data and busloads become large.

Therefore, a data communication system between single-chip microcomputers, which is common today, will be explained with reference to FIG. Multiprocessor systems of the drawings using single-chip microcomputers usually have serial or parallel interfaces (
40), and the communication protocol is as follows: (1) The master/slave processor (3) sets the input/output port (40) to input mode. , other processors (
Wait for data communication in 1).

(2> Processor (3) input/output interface (4)
0) outputs an interrupt request upon receiving address data.

(3) The processor (3) determines whether the address data received by the interrupt process specifies itself.

(4) The designated processor (3) then receives the data and, if necessary, executes a predetermined interrupt process after executing the interrupt process branch routine.

That is what it is.

However, in this data communication method, even when communicating between specific processors, each processor determines whether or not it is designated by interrupt processing, and interrupt requests are frequently made between specific processors. In a system in which this occurs or in a large-scale system, each processor has the disadvantage of being busy with interrupt processing for determination. Furthermore, in order to deal with multiple interrupt causes, an interrupt processing branch routine must first be executed, which has the disadvantage of slowing down processing speed and placing a heavy burden on the software required to distinguish between interrupt causes. .

(c) Problems to be Solved by the Invention The present invention eliminates the need for other processors to process interrupts in the case of specific inter-processor communication, and furthermore quickly responds to multiple interrupt causes without burdening software. An object of the present invention is to provide a single-chip microcomputer with an interrupt function capable of interrupting.

(d) Means for Solving the Problems In order to solve the above-mentioned problems, the single-chip microcomputer of the present invention has a first program counter (31
), a second program counter (3o), address data that outputs an interrupt request (44) and is received at the input/output port based on an interrupt response to the interrupt request, and the first program counter (3o); and an address selection circuit (42) for selectively loading the data of 31) into the second program counter (30).

(*) Effect The configuration of the present invention described above is based on the first program counter (
The execution address is determined by a second program counter (30) into which the data of 31) is loaded in parallel;
The address selection circuit (42) issues an interrupt request (
44), and then waits for an interrupt response (45) and loads the address data of the input/output port (40) into the second program counter (30) in place of the data in the first program counter (31). Therefore, it acts to transfer the control of the processor to that address.

(F) Embodiment Referring to FIG. 1, the present invention will be described in detail by taking inter-processor data communication as an example. In the figure, (3) is a single-chip microcomputer of the present invention. For convenience, this will be referred to as a slave processor, and processor (1) will be referred to as a mask processor.

The execution address of the slave processor (3) is determined by the second program counter (30) into which the data of the first program counter (31) is loaded in parallel, and the input/output port (41) is controlled by the original program processing. Data datl and dat2 are used to control devices (not shown) through the mask processor (1)
...... is generated and updated, and the data dat is generated and updated each time.
l to address 0OOOH of RAM (33) and dat2 to 000
They are stored in order such as address 1H.

Then, for example, at address 0030H of the ROM (32) of the slave processor (3), "ooo of RAM (33).

An instruction to "output the data at address H to the input/output port (40)" is written, and at address 0038H of the ROM (32), "to output the data at address 0OOIH of the RAM (33) to the input/output port (
40) can be written, and a plurality of instructions are similarly written in the ROM (32).

Therefore, when the mask processor (1) needs the data dat2 of the slave processor (3) to perform its own program processing, it first transfers the chip select data or control signal for chip selection to the system bus (2). Output to.

An address selection circuit (42) comprising a programmable decoder or simply one bit of a register then generates an interrupt based on the particular chip select data received by said input/output port (40) or directly from a control signal. Generate a request (44). The above operation is performed independently of the processor function, and the slave processor (3) can continue its own program during this time. Further, it is naturally possible for other processors (not shown) to continue their own programs after this point.

When the address selection circuit (42) detects chip select data that specifies itself or outputs an interrupt request (44) by the mount control signal, the slave processor (
3) interrupts the program being processed and starts a predetermined interrupt procedure. Here, the single-bump microcomputer of the present invention is distinctive in that it does not require saving the program counter and interrupt procedures can be performed faster.

When an interrupt response (45) is thus obtained, an interrupt response flag is set in the interrupt flag register (43).

When the master processor (1) detects the interrupt response flag by any means, it then outputs 8-bit address data 38H which becomes an interrupt vector. It should be noted that if the load control signal can be used for chip selection, the interrupt vector 38H can be output at the same time as the control signal, and the processing speed can be further improved.

The address selection circuit (42) that received the interrupt response (45) generates 16-bit address data 0038H from the 8-bit address data of the input/output port (40) by index designation or other known means, and also outputs the first program. counter (31) to the second program counter (30)
and loads said address data into a second program counter (30). Also, at this time, it is natural that the program counter controlled by the instruction decoder (38) is changed from the first program counter (31) to the second program counter (30). As a result, the slave processor (3) transfers control to address 0038H, and the "0OOI" of the RAM (33) written there.
Output the data at address H to the input/output port <40) °'
All instructions can be executed.

When the data dat2 is thus output to the input/output port, the mask processor (1) can learn the value of the data dat2 via the system bus (2) and continues its own program processing that requires this data. However, in the above communication method, the slave processor (3)
If the master processor (1) needs it before it generates data, say dat2, then the mask processor (1)
1) It can be expected that the interrupt vector 38H will be output more continuously and will interfere with the process of generating data dat2 of the slave processor (3), but this problem is caused by interrupt vectors that did not output data This can be resolved by taking measures such as not accessing the site for a certain period of time.

When the single-chip microcomputer of the present invention is used as described above, any data requested by the processor can be obtained from other processors at any time.
There is no need to reserve a data area for the processor, and a particularly remarkable effect can be expected when constructing a multiprocessor system using a single-chip microcomputer with relatively limited RAM capacity.

(g) Effects of the Invention The single-chip microcomputer of the present invention does not need to use interrupt processing to determine whether address data is specified for itself each time it is sent from another processor. There is no program interruption, and since interrupt vectors are provided via an 8-bit bus, it is possible to quickly respond to an unlimited number of interrupt requests.
Suitable for use in multiprocessor systems.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a multiprocessor system using a single-chip microcomputer according to the present invention, and FIG. 2 is a block diagram of a multiprocessor system using a conventional single-chip microcomputer. (1) and (3) are single-chip microcomputers, (2) is a system bus, (30) is a second program counter, 31) is a first program counter, (
32) is ROM, (33) is RAM, (34) is accumulator, (35) is - hour register, (36) is arithmetic logic unit, (37) is flag register, (38) is instruction decoder, ( 39) is an internal bus, (40) and (4
1) is an input/output interface, (42) is an address selection circuit, (43) is an interrupt flag register, (44) is an interrupt request, and (45) is an interrupt response.

Claims (1)

[Claims] (1) Two program counters, a first and a second program counter, and address data that outputs an interrupt request and is received at an input/output port based on an interrupt response to the interrupt request, and the first program counter. and an address selection circuit that selectively loads data into the second program counter.