JPH0367357A - Multi-cpu system - Google Patents

Abstract

PURPOSE:To facilitate the generation of a program by performing data processing between plural processing parts which have CPUs through a common memory. CONSTITUTION:The CPU 4 of a processing part 1 inputs data through a peripheral device 7 and checks whether or not a processing part 2 is using the common memory 3. When a memory 6 is writable, data are written in order and when not, the peripheral device 7 is inhibited from inputting data. When the use of the common memory 3 by the processing part 2 is finished, the inputted data are transferred and stored. The CPU 10 of the processing part 2 reads and processes the data after the input processing of the processing part 1. Various data processes are performed without saving and loading data in and from registers, the processing speed can be made fast, and the generation of the program is facilitated.

Description

DETAILED DESCRIPTION OF THE INVENTION <Field of Industrial Application> The present invention relates to a multi-CPU system in which processing is executed by a plurality of CPUs.

<Prior art> Generally, in a system using a CPU, one C
Systems are often constructed using a so-called single CPU method using a PU.

FIG. 7 is a block diagram showing an example of a system configuration of such a single CPU system.

The system shown in this figure has one CPU101 and this C
Memory 1 such as ROM that stores the PUl0I program
02, a memory 103 such as a RAM used as a work area for the CPU 101, and a peripheral device 104 that inputs and outputs signals to the outside.
Various processes are executed based on programs stored in 2.

In this case, if the content described by the program is a subroutine process, the process is executed according to the procedure shown in FIG.

In this process, the CPU 101 first stores the current execution address as an address (return address) necessary for returning from the subroutine (step 5TIOI), and then jumps to the starting address of the subroutine (step 5T102).

In this subroutine, the CPU 101 first saves the values of each register inside the CPU to the stack area of the memory 103 (step 5T103).

After this, the CPU 10I performs the processing specified by the subroutine, for example, the processing of fetching data from the peripheral device 104 and storing it in a register (step 5T10).
4) After performing processing such as transferring data from this register to the memory 103 (step 5T105), the multi-value saved in the stack area is returned to the register (step 5T106).

Next, CPUl01 reads the value of the stored return address (step 5T107), jumps to the address indicated by this value, and returns to the main routine (step 5T107).
108).

Then, the process described in this main routine, such as the process of transferring the value fetched in the subroutine to the register, is performed (step 5T109).

Also, if the content described in the program is an interrupt process, the process is executed according to the procedure shown in FIG.

In this process, the CPU 101 first receives an interrupt request output from the peripheral device 104, updates the interrupt mask in accordance with this interrupt request, and prevents an interrupt having a lower priority than this interrupt request from occurring (step 5TIIO).

After this, CPUl0I requests a vector number from the peripheral device 104, and when this is output, it generates an interrupt vector corresponding to this vector number (step 5T
12) The values of the program counter and each register inside the CPU are saved to the stack area of the memory 103 (step 5T113).

Thereafter, the CPULOI calculates the start address of the interrupt processing routine corresponding to this interrupt vector based on the interrupt vector (Step 5T114), and sets this in the program counter (Step S114).
T5) Jump to the address of the value written in this program counter and execute the process described at this address (steps 5T116 and 5T117).

When this processing is completed, the CPULOI releases the interrupt request from the peripheral device 104, returns the multivalues saved in the stack area to the program counter and each register (step 5T118), and ends the interrupt processing. .

In this way, in this system, one CPU10
I sequentially selects and executes subroutine processing, interrupt processing, etc.

However, in such a system, when moving from the main routine to a subroutine or interrupt processing routine, or from a subroutine or interrupt processing routine to the main routine, the contents of each register inside the CPULOI must be saved to the stack area and restored. Therefore, there is a problem in that extra time is required to perform these processes, and the execution speed becomes slow.

Furthermore, a stack area must be secured on the memory 103 or the like, making memory management complicated.

In addition, in order to perform interrupt processing, it is necessary to manage the starting address of the area where the interrupt processing program is stored, which makes the program creation work that much more complicated.

Purpose of the present invention In view of the above-mentioned circumstances, the present invention is designed to omit the process of saving and restoring registers, etc. when moving from a main routine to a subroutine, etc., or when moving from this subroutine etc. to the main routine, and execute only that amount of processing. A multi-CPU that can increase speed and eliminate the need to manage stack areas and interrupt processing addresses, making it easier to create programs.
The purpose is to provide a system.

<Configuration> In order to solve the above problems, a multi-CPU according to the present invention
In the system, a plurality of processing units each having a CPU;
It is characterized in that it is provided with a common memory used as a common memory for each of these processing sections, and that data is exchanged between the processing sections via the common memory.

Hereinafter, the present invention will be specifically explained based on one example.

The first drawing is a block diagram showing an embodiment of a multi-CPU system according to the present invention.

The multi-CPU system shown in this figure has two processing units,
2 and one common memory 3, the processing section performs data input/output processing, and the processing section 2 performs other processing.

The processing unit includes one CPU 4, a memory 5 such as a ROM in which the program of this CPU 4 is stored, and the CPU 4.
A memory 6 such as a RAM used as a work area for the CPU 4, a peripheral device 7 used as an input/output device for the CPU 4, a data bus 8 and an address bus connecting the CPU 4 to the peripheral device 7 and the common memory 3. 9, it exchanges data with an external device according to the program stored in the memory 5, and performs various processes using the memory 6 as a work area.

In addition, the processing unit 2 includes one CPUl0 and this CPUl0.
A memory 11 such as a ROM in which programs are stored, and R A used as a work area for the CPU10.
Memory 12 such as M, and these CPU10~memory 12
and a data bus 13 connecting the common memory 3.
It is equipped with an address bus 14, and exchanges data with the common memory 3 according to a program stored in the memory earthwork, and performs various processes using the memory 12 as a work area.

In addition, the common memory 3 has two independent input/output units, and stores data output from each of the processing units 2 and reads stored data and transfers it to each processing unit 2. .2.

Next, the data input operation and data processing operation of this embodiment will be explained with reference to the flowcharts shown in FIGS. 2 and 3.

First, in the data input operation, as shown in FIG. (Step 5T2).

If the common memory 3 is being used by the processing unit 2, the CPU 4 checks whether the memory 6 is writable (step 5T3), and if it is writable, transfers the data taken in by the peripheral device 7 to the memory 6.
Transfer and store the 1e data to (step 5T2.5T5)
.

Further, if the memory 6 is not writable, the CPU 4
issues an input prohibition command to the peripheral device 7 to stop data capture (step 5T6).

After this, when the processing unit 2 finishes using the common memory 3,
The CPU 4 transfers the data stored in the memory 6, that is, the data taken in via the peripheral device 7, to the common memory 3, and stores the data in the common memory 3 (step 5T7).

In addition, in parallel with this data input operation, the CP on the processing unit 2 side
After processing the previous process as shown in FIG. 3 (step 5TIO), Ul0 reads the data written by the processing unit 1 from the common memory 3 (step 5T).
12), which will be processed by subsequent processing (step 5).
T12).

In this embodiment, the processing unit 1 performs data input processing, and the processing unit 2 processes the input data, so data can be input without performing save processing or restoration processing of the register, etc. It is possible to perform input/output processing and various data processing, thereby increasing the execution speed of processing, as well as omitting the management of stack areas, making it easier to create programs.

FIG. 4 is a block diagram showing another embodiment of the multi-CPU system according to the present invention.

The multi-CPU system shown in this figure has three processing units
10.a, 10b, and 1, one common memory 13, and a selection section 4. Processing sections 10 and 11 perform data input/output processing, and processing section 1 performs other processing.

Each of the processing units 10a and 10b includes one CPU 15, a memory 16 such as a ROM in which a program for the CPU 15 is stored, a memory 17 such as a RAM used as a work area for the CPU 15, and an input for the CPU 5. Peripheral devices used as output devices and these CPU1
5 to peripheral devices 18 and a data bus 19 and an address bus 20 that connect the selection unit 14, respectively.

Data is exchanged with the selection section 14 and each external device according to programs stored in each memory 16, and various processes are performed using the memory 17 as a work area.

The processing unit 11 also includes a CPU 25 and a CPU 2.
Memory 26 such as ROM in which the program No. 5 is stored
and a data bus 27 and an address bus 28 that connect these CPU 25, memory 26, and common memory 13.
It exchanges data with the common memory 3 according to the program stored in the memory 26, and performs various processes based on the various data stored in the common memory 13.

Further, the common memory 13 has two independent input/output sections, and stores data output from the processing section 1 and the selection section 14, and reads out stored data and transfers it to the processing section 1. 11 and the selection unit 14.

The selection unit 14 controls permission/disapproval of connection between each of the processing units 10a, 10b and the common memory 13, a warpage control circuit 30, and a response signal IRQ of this memory control circuit 30.
-B, and an inverter 31 that inverts the response signal IRQ-A to generate the response signal IRQ-A, and each of these response signals IRQ-A and IRQ-B.
a data select circuit 32 that selects one of the data buses 19 constituting each of the processing units 10a and 10b based on the response signals IRQ-A and IRQ·B; 10b, and a data select circuit 33 for selecting one of the address buses 20 constituting the respective processing units 10a-10b.
When an interrupt request is received from the common memory 13, it is checked whether or not the common memory 13 is writable, and if it is writable, the data bus 9 and address bus 20 of the processing section issuing the interrupt request are transferred to the common memory. Connect to 13.

Next, the operation of this embodiment will be explained with reference to the flowcharts shown in FIG. M5 and FIG.

First, any one of the peripheral devices 18, for example, the processing unit 10a
When there is an input to the peripheral device 18, the CPU15 of the processing unit Oa detects this and issues an interrupt request signal INT-
A is generated and supplied to the memory control circuit 30 of the selection section 4 (step S 5).

As a result, the memory control circuit 3o checks whether the common memory 13 is currently being used by the processing unit 1 or the processing unit 10b, and if it is, it sends a response signal I RQ-A indicating that data transmission is not possible. The raw material is then supplied to the CPU 15 of the processing section 10a.

When the CPU 15 of the processing unit 10a receives this response signal IRQ-A, it determines that it is currently impossible to write to the common memory 13 (step 5T16).

After this, the CPU 15 of the processing section 10a checks whether the memory 17 of its own processing section 10a is writable (Step 5T17), and if it is writable, the peripheral device 1
8 is sequentially transferred to and stored in the memory 17 (steps 5T18 and 5T19).

Further, if the memory 17 is not writable, the CPU 15 of the processing unit 10a issues an input prohibition command to the peripheral device 18 to stop data capture (step 5).
T20).

After that, when the processing unit 11 or the processing unit 10b finishes using the common memory 13, the memory control circuit 3° detects this and sends a response signal IRQ-B indicating permission to use the common memory 13.
is generated and supplied to the CPU 15 of the processing unit l○a and each data selection circuit 32, 33.

As a result, each data select circuit 32.33 is connected to the data bus 19.3 of the processing section 10a. At the same time as selecting the address bus 20, the cPU 15 of the processing section 10a transfers the data stored in the memory F, that is, the data taken in via the peripheral device 18, to each data selector circuit of the selection section 14.
32.33, common memory 1 via memory control circuit 30
3 and stores it in this common memory 13 (step 5T21).

In addition, in parallel with this data input operation, the C
After processing the previous process as shown in FIG. 6 (step 5T25), the PU 25 reads the data written by the processing unit 10a from the common memory 13 (step 5T21), and processes this in the subsequent process. (
Step 5T27).

As described above, in this embodiment, the processing section Oa, 10
Since the data input processing is performed by b and the input data is processed by the processing unit 11, the saving processing and restoring processing of registers etc. are omitted and the processing is executed accordingly, as in the above-mentioned embodiment. The speed can be increased, and the management of stack areas and interrupt processing destination addresses can be omitted, thereby making it easier to create programs.

<Effects> As explained above, according to the present invention, when moving from a main routine to a subroutine, etc., or when moving from this subroutine etc. to the main routine, saving processing of registers, etc.
By omitting the return process, the execution speed of the process can be increased accordingly, and the management of the stack area and the address of the interrupt processing destination can be omitted, thereby making it easier to create programs. I can do it.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a multi-CPU system according to the present invention, and FIG. 2 is a block diagram showing an embodiment of the multi-CPU system according to the present invention.
3 is a flowchart showing an example of data input operation of the system; FIG. 3 is a flowchart showing an example of data processing of the multi-CPU system shown in FIG. 1; FIG. 4 is a block diagram showing an embodiment of the multi-CPU system according to the present invention; 5 is a flowchart showing an example of data input operation of the multi-CPU system shown in FIG. 4, and FIG.
FIG. 7 is a block diagram showing an example of a conventionally known single CPU system; FIG. 8 is a flowchart showing an example of subroutine processing of the system shown in FIG. 7; This figure is a flowchart showing an example of interrupt processing of the system shown in FIG. 1.2... Processing unit, 3... Common memory, 4.1o.
...CPU, 5...Memory, 7...-Peripheral device.

Claims (1)

[Claims] (1) Equipped with a plurality of processing units each having a CPU and a common memory used as a common memory for each of these processing units,
A multi-CPU system characterized in that data is exchanged between each processing unit via the common memory.