JPH0240954A - Master slice semiconductor integrated circuit - Google Patents

Master slice semiconductor integrated circuit

Info

Publication number
JPH0240954A
JPH0240954A JP63191674A JP19167488A JPH0240954A JP H0240954 A JPH0240954 A JP H0240954A JP 63191674 A JP63191674 A JP 63191674A JP 19167488 A JP19167488 A JP 19167488A JP H0240954 A JPH0240954 A JP H0240954A
Authority
JP
Japan
Prior art keywords
circuit
external
external terminal
semiconductor integrated
master slice
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63191674A
Other languages
Japanese (ja)
Inventor
Teruo Matsuba
松葉　輝生
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63191674A priority Critical patent/JPH0240954A/en
Publication of JPH0240954A publication Critical patent/JPH0240954A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/901—Masterslice integrated circuits comprising bipolar technology

Landscapes

  • Logic Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 ［産業上の利用分野］ 本発明はマスタースライス方式半導体集積回路に関し、
特に、エミッタ結合論理回路（以下、ＥＣＬ回路という
）により構成されるマスタースライス方式半導体集積回
路に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a master slice type semiconductor integrated circuit,
In particular, the present invention relates to a master slice type semiconductor integrated circuit constituted by an emitter-coupled logic circuit (hereinafter referred to as an ECL circuit).

［従来の技術］ 従来から、ＬＳＩチップ構成法の一つとしてマスタース
ライス方式が知られている。マスタースライス方式半導
体集積回路は、所望の機能を実現するための内部回路と
、この内部回路と外部端子とを電気的に接続する外部回
路とからなり、予め用意されたいくつかの機能を持つ内
部回路を外部回路で選択することにより所望の回路を実
現するものである。マスタースライス方式では、通常、
内部回路及び外部回路を共にＥＣＬ回路により構成する
。特に、外部回路は外部端子に接続される負荷を駆動す
るため大電流を流す必要があった。[Prior Art] A master slice method has been known as one of LSI chip construction methods. A master slice semiconductor integrated circuit consists of an internal circuit to achieve a desired function and an external circuit that electrically connects this internal circuit to an external terminal. A desired circuit is realized by selecting the circuit using an external circuit. In the master slice method, typically
Both internal and external circuits are constructed from ECL circuits. In particular, the external circuit required a large current to flow in order to drive the load connected to the external terminal.

［発明が解決しようとする課題］ 上述した従来のマスタースライス方式半導体集積口′路
は、外部回路がＥＣＬ回路により構成され、且つ、負荷
を駆動する関係上消費電力が大きい。[Problems to be Solved by the Invention] In the above-described conventional master slice type semiconductor integrated circuit, the external circuit is constituted by an ECL circuit, and power consumption is large because the external circuit is configured to drive a load.

一方、回路の品質保証という点からは、この種の回路で
も試験用の外部モニタ端子を設ける必要がある。しかし
ながら、上述したように外部回路の消費電力が大きいの
で試験のためだけの外部モニタ端子を設けると、結局、
その分、外部回路も使用されるので、チップ全体として
消費電力が増加するという欠点があった。On the other hand, from the point of view of circuit quality assurance, it is necessary to provide an external monitor terminal for testing even in this type of circuit. However, as mentioned above, the power consumption of the external circuit is large, so if an external monitor terminal is provided just for testing, the
Since an external circuit is also used, there is a drawback that the power consumption of the chip as a whole increases.

本発明はかかる問題点に鑑みてなされたものであって、
テスト用の外部モニタ端子を設けてもチップ全体の消費
電力を増加させることがないマスタースライス方式半導
体集積回路を提供することを目的とする。The present invention has been made in view of such problems, and includes:
An object of the present invention is to provide a master slice type semiconductor integrated circuit that does not increase the power consumption of the entire chip even if an external monitor terminal for testing is provided.

［課題を解決するための手−段コ 本発明に係るマスタースライス半導体集積回路は、エミ
ッタ結合論理回路からなる内部回路と、第１及び第２の
外部端子と、前記内部回路と前記第１の外部端子とを電
気的に接続するエミッタフォロワトランジスタからなる
外部回路と、この外部回路のエミッタフォロワトランジ
スタのベースと前記第２の外部端子との間に接続され、
前記ベース側をカソード、前記第２の外部端子側をアノ
ードとするダイオードとを具備したことを特徴とする。[Means for Solving the Problems] A master slice semiconductor integrated circuit according to the present invention includes an internal circuit comprising an emitter-coupled logic circuit, first and second external terminals, and the internal circuit and the first external terminal. an external circuit consisting of an emitter follower transistor electrically connected to an external terminal, and an external circuit connected between the base of the emitter follower transistor of this external circuit and the second external terminal,
The device is characterized by comprising a diode having the base side as a cathode and the second external terminal side as an anode.

［作用コ 本発明によれば、第２の外部端子にＬレベル電圧が印・
加されると、ダイオードは非導通状態となり、外部回路
がアクティブ状態となって、第１の外部端子をモニタ端
子として使用できるようになる。[Function] According to the present invention, an L level voltage is applied to the second external terminal.
When the voltage is applied, the diode becomes non-conducting, the external circuit becomes active, and the first external terminal can be used as a monitor terminal.

また、第２の外部端子にＨレベル電圧が印加されると、
ダイオードは導通状態となり、外部回路はエミッタフォ
ロワのベースが高電圧に固定されるので、第１の外部端
子も高電位固定となる。このため、実使用時には第１の
外部端子は、内部回路に何ら影響を与えず、消費電力も
抑制される。Furthermore, when an H level voltage is applied to the second external terminal,
The diode becomes conductive and the base of the emitter follower of the external circuit is fixed at a high voltage, so the first external terminal is also fixed at a high potential. Therefore, during actual use, the first external terminal does not have any influence on the internal circuitry, and power consumption is also suppressed.

［実施例コ 以下、本発明の実施例について添付の図面を参照して説
明する。[Embodiments] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

第１図は本発明の実施例に係るマスタースライス方式半
導体集積回路の部分的な回路図である。FIG. 1 is a partial circuit diagram of a master slice type semiconductor integrated circuit according to an embodiment of the present invention.

内部回路１のＥＣＬ回路を構成するエミッタフォロワト
ランジスタ１１の出力は外部回路２の抵抗１２を介して
エミッタフォロワトランジスタ１３のベースに接続され
ている。エミッタフォロワトランジスタ１３は第１の外
部端子３を駆動する。The output of the emitter follower transistor 11 constituting the ECL circuit of the internal circuit 1 is connected to the base of the emitter follower transistor 13 via the resistor 12 of the external circuit 2. Emitter follower transistor 13 drives first external terminal 3 .

また、エミッタフォロワトランジスタ１３のベースには
ダイオード１４のカソードが接続されている。ダイオー
ド１４のアノードは第２の外部端子４に接続されている
。Furthermore, a cathode of a diode 14 is connected to the base of the emitter follower transistor 13. The anode of the diode 14 is connected to the second external terminal 4.

以上の構成であると、第１の外部端子３は第２の外部端
子４が内部回路１のエミッタフォロワトランジスタ１１
のエミッタ電位以下に設定されているときは、モニタ端
子として使用でき、第２の外部端子４が接地されたとき
は高電位固定となる。With the above configuration, the first external terminal 3 and the second external terminal 4 are connected to the emitter follower transistor 11 of the internal circuit 1.
When the emitter potential is set below the emitter potential of , it can be used as a monitor terminal, and when the second external terminal 4 is grounded, the potential is fixed at a high potential.

［発明の効果］ 以上、説明したように本発明は第２の外部端子からダイ
オードを通じてエミッタフォロワトランジス、夕のベー
ス電位を制御することにより、テストモードと通常使用
モードとを外部から切換えられるようにしているので、
実使用時に殆ど消費電力を増加させることなく、内部モ
ニタのための外部端子を設けることができるという効果
がある。[Effects of the Invention] As explained above, the present invention enables switching between the test mode and the normal use mode from the outside by controlling the base potential of the emitter follower transistor and the base of the emitter follower transistor through the diode from the second external terminal. Because
This has the advantage that an external terminal for internal monitoring can be provided without substantially increasing power consumption during actual use.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の実施例を示す回路図である。 １；内部回路、２；外部回路、３；第１の外部端子、４
；第２の外部端子、１１．１３．エミッタフォロワトラ
ンジスタ、１２；抵抗FIG. 1 is a circuit diagram showing an embodiment of the present invention. 1; Internal circuit, 2; External circuit, 3; First external terminal, 4
; second external terminal, 11.13. Emitter follower transistor, 12; resistor

Claims (1)

【特許請求の範囲】[Claims] （１）エミッタ結合論理回路からなる内部回路と、第１
及び第２の外部端子と、前記内部回路と前記第１の外部
端子とを電気的に接続するエミッタフォロワトランジス
タからなる外部回路と、この外部回路のエミッタフォロ
ワトランジスタのベースと前記第２の外部端子との間に
接続され、前記ベース側をカソード、前記第２の外部端
子側をアノードとするダイオードとを具備したことを特
徴とするマスタースライス方式半導体集積回路。(1) An internal circuit consisting of an emitter-coupled logic circuit and a first
and a second external terminal, an external circuit comprising an emitter follower transistor electrically connecting the internal circuit and the first external terminal, and a base of the emitter follower transistor of this external circuit and the second external terminal. 1. A master slice type semiconductor integrated circuit, comprising: a diode connected between the first and second external terminals and having the base side as a cathode and the second external terminal side as an anode.
JP63191674A 1988-07-31 1988-07-31 Master slice semiconductor integrated circuit Pending JPH0240954A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63191674A JPH0240954A (en) 1988-07-31 1988-07-31 Master slice semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63191674A JPH0240954A (en) 1988-07-31 1988-07-31 Master slice semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPH0240954A true JPH0240954A (en) 1990-02-09

Family

ID=16278570

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63191674A Pending JPH0240954A (en) 1988-07-31 1988-07-31 Master slice semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPH0240954A (en)

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