JPH0240965A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To facilitate the control of a gate region by a method wherein, when two gate-regions of a dual gate junction type field effect transistor are formed, windows are formed by one time lithography working, and impurity is implanted in one of the gate regions, through a polycrystalline silicon layer. CONSTITUTION:A window is formed by etching an oxide film 6 on the surface of a substrate 1, and a source region 4 and a drain region 5 are formed by introducing N<+> type impurity; by lithography art, openings are formed simultaneously in a film 6 of the parts corresponding with a first and a second gate regions 8 and 9; a polycrystalline silicon layer 7 is formed on the whole surface: this layer 7 is etched and left on the opening part corresponding with a second gate region 9 and on the film 6, so as to be larger than the opening part by several mum; the regions 8 and 9 are simultaneously formed by boron ion implantation or the like. Thereby, the region 9 is formed to a depth shallower than the region 8; relative position gap between the regions 8 and 9 can be eliminated; the control of gate region is facilitated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and in particular to a dual-gate junction field effect transistor having a structure having two gates between a source and a drain suitable for high frequency amplification. J-
FET) manufacturing method.

(Prior Art) In general, a dual gate J-FET is represented by the equivalent circuit shown in FIG. The gate (second gate) is connected to the source of the other J-FET.

A conventional manufacturing method of this type of dual gate J-FET is shown in FIGS. 3(a) to 3(e).

First, as shown in FIG. 3A, an n-type semiconductor layer 2 is epitaxially grown on the main surface of a p-type semiconductor substrate l, and a p A diffusion layer 3 is formed.

Then, the oxide film 6 on the surface of the semiconductor substrate is selectively etched to form a window, and an n-type impurity is introduced from the window to form a source region 4 and a drain region 5 made of n'-type semiconductor regions.

Next, as shown in FIG. 3(b), the oxide film is regrown and a window is opened again to form a first gate region 8 made of a p-type semiconductor region, and the depth of the diffusion layer is controlled. do.

Thereafter, a second gate region 9 made of a p-type semiconductor region is formed by the same process as shown in FIG. 3(c), and the depth of the diffusion layer is further controlled to control the characteristics. At this time, a p° semiconductor region 10 for making contact with the p° layer 3 is formed at the same time.

Note that in a normal dual-gate J-FET, in order to have good voltage reduction characteristics, the depth of the diffusion layer in the first gate region 8 is set to be approximately greater than the depth of the diffusion layer in the second gate region 9. It is controlled to a depth of 0.2 to 0.8 μm.

Thereafter, as shown in FIG. 3(d), the oxide film 6 on each region is removed by etching, and then, as shown in FIG. 3(e), an aluminum electrode 11 is formed to make contact with each region. The dual gate J-FET shown in FIG. 4 is manufactured by connecting the wires as shown in the figure.

[Problems to be Solved by the Invention] In the conventional method for manufacturing a dual-gate J-FET described above, the depths of the diffusion layers of the first gate region 8 and the second gate region 9 are controlled separately, so that it is difficult to control the depth of the diffusion layer. There is a problem in that it takes a lot of man-hours.

Furthermore, when forming the first gate region 8 and the second gate region 9, the oxide film 6 is opened separately using lithography technology, but the dimensions of each part of the dual gate J-FET are determined by the gate length of the first gate. The gate length of the second gate is 0.8 to 1.5 μm, and the gate length of the second gate is 2 to 6 μm, which is designed to have a spacing of about 8 to 15 μm. The problem is that relative positioning between two lithographic operations is very difficult.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a semiconductor device that facilitates the manufacture of a first gate region and a second gate region.

[Means to solve the problem]

The method for manufacturing a semiconductor device of the present invention includes the steps of simultaneously opening windows in the insulating film at locations corresponding to the first and second gate regions, and forming a polycrystalline silicon layer to cover the windows in the gate region on the shallow side. and simultaneously implanting impurities through each of the windows to form first and second gate regions and controlling the depth thereof.

[Effect]

In the above-described manufacturing method, the opening when forming the first and second gate regions can be performed in one lithography operation, and a fine gate can be realized by eliminating relative positional deviation between the two regions. Furthermore, since impurities are implanted into one gate region through the polycrystalline silicon layer, one gate region can be automatically formed shallower than the other, making it easier to control the gate region.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 1(a) to 1(e) are longitudinal sectional views showing a first embodiment of the method for manufacturing a dual gate J-FET according to the present invention in order of steps.

First, as shown in FIG. 1(a), an n-type semiconductor layer 2 is epitaxially grown on the main surface of a P-type semiconductor substrate 1, and a p-diffusion layer is applied thereto to connect the source and second gate regions to the back surface, which will be described later. Form layer 3.

Then, the oxide film 6 on the surface of the semiconductor substrate is selectively etched to form a window, and an n-type impurity is introduced from the window to form a source region 4 and a drain region 5 comprising n°-type semiconductor regions. Thereafter, the oxide film 6 at locations corresponding to the first gate region and the second gate region are simultaneously opened using lithography technology.

Next, as shown in Figure 1(b), 2000 to 80
A polycrystalline silicon layer 7 with a thickness of 0.00 mm is formed, and this polycrystalline silicon layer 7 is etched over the opening of the oxide film 6 corresponding to the second gate region so as to remain several μm larger than the opening. do. At this time, a portion of the polycrystalline silicon layer 7 is also left in the contact area of the p diffusion layer 3.

Then, as shown in FIG. 1C, a first gate region 8 and a second gate region 9 made of p-type semiconductor regions are simultaneously formed by boron ion implantation or BCf3 diffusion,
The depth of the diffusion layer in each gate 6N region is controlled. At this time, the second
Gate region 9 is formed shallower than first gate region 8 . Incidentally, at this time, a p' type semiconductor region 10 is also formed in the P1 diffusion layer 3 at the same depth as the second gate region 9.

Therefore, by appropriately controlling the film thickness of polycrystalline silicon layer 7, ion implantation energy, etc., it is possible to arbitrarily set the depth of each gate 6i region 8.9.

Then, as shown in FIG. 1(d), contact windows are opened in the required locations of the oxide film 6, and then an aluminum film is formed on the entire surface as shown in FIG. 1(e), and this is selectively etched. By doing so, an aluminum electrode 11 is formed.

Then, by connecting as shown in the figure, a dual J-FET is completed.

Therefore, in this manufacturing method, when forming the first gate region 8 and the second gate SN region 9, openings in the oxide film 6 corresponding to both gate regions are performed in one step, so the first. Relative positional deviation between the second gate regions can be almost eliminated, and fine gate dimensions can be realized. In addition, the depth of the diffusion layer of the first and second gate regions can be made shallower on the second gate region 9 side by the polycrystalline silicon layer 7, so the diffusion depth of both gate regions can be controlled simultaneously, making the control work easier. It can be made into something.

FIGS. 2(a) and 2(b) are longitudinal cross-sectional views showing the main steps of a second embodiment of the present invention. Note that the steps shown in FIG. 1(a) to FIG. 1(c), that is, the steps up to simultaneously forming the first gate M region 8 and the second gate region 9, are the first step.
This is exactly the same as the embodiment, and illustration thereof is omitted.

In this embodiment, after forming the first and second gate regions 8°9, as shown in FIG.
゛Polycrystalline silicon layer 7 left on semiconductor region 10
is being removed.

After that, a contact portion is opened in the oxide film 6 and an aluminum electrode 11 is formed, as shown in FIG. 2(b).
A dual J-FET shown in can be manufactured.

In this embodiment, since the aluminum electrode 11 is not formed on the polycrystalline silicon layer 7, there is an advantage that disconnection of the aluminum wiring, which tends to occur at the stepped portion of the polycrystalline silicon layer, can be avoided.

〔Effect of the invention〕

As explained above, in the present invention, when forming the first gate region and the second gate region, openings in the insulating film corresponding to both gate regions are performed in a single process.
．． 2nd game)? Relative positional deviation between the J regions can be almost eliminated, and fine gate dimensions can be realized. Also, 1st. Since the depth of the diffusion layer in the second gate region can be made shallower in one gate SN region than the other gate region by the polycrystalline silicon layer, the diffusion depth in both gate regions can be controlled simultaneously. It has the effect of making work easier.

[Brief explanation of the drawing]

1(a) to 1(e) are longitudinal sectional views showing the first embodiment of the manufacturing method of the present invention in the order of steps, and FIG. 2(a) and FIG. FIG. 3(a) to FIG. 3(e) are vertical sectional views showing the manufacturing method of the conventional dual-gate J-FET in the order of steps; FIG. 4; is an equivalent circuit diagram of a dual gate J-FET. DESCRIPTION OF SYMBOLS 1...p-type semiconductor substrate, 2...n-type semiconductor region (epitaxial layer), 3...p゛diffusion layer, 4...n゛semiconductor region (source region), 5...n゛Semiconductor area (
drain region), 6... oxide film, 7... polycrystalline silicon layer, 8... p' semiconductor region (first gate region),
9...p semiconductor region (second gate region), 10...
・p゛Semiconductor region (contact region), 11...aluminum electrode.

Claims (1)

[Claims] 1. In a method for manufacturing a dual-gate junction field effect transistor having first and second gate regions configured at different depths between a source region and a drain region, the method corresponds to the first and second gate regions. a step of forming a polycrystalline silicon layer to cover the windows in the gate region on the shallow side; and a step of simultaneously injecting impurities through each of the windows to form the first and first windows. 1. A method of manufacturing a semiconductor device, comprising: forming a second gate region and controlling the depth thereof.