JPH0241694Y2 - - Google Patents

Description

[Detailed explanation of the idea]

[Industrial Application Field] The present invention relates to an asynchronous data write/read circuit. [Prior Art] Recently, digital signal processing technology has been increasingly applied to consumer electrical equipment. For example, signals detected from a controlled system (asynchronous data) are
Memory (hereinafter referred to as RAM) can be sequentially written to a specified address, and stored asynchronous data can be read out sequentially and treated as data synchronized to a certain frequency, or the controlled system can be controlled by measuring the asynchrony of writing and reading. Control is being done. There are various types of systems to be controlled, and for example, there is a rotating system of an optical digital audio disc player. This rotating system sequentially writes signals (asynchronous data) read from the optical digital audio disk into designated addresses in the RAM, and reads out the stored data at regular intervals. Further, it has a configuration in which this asynchrony is measured and a motor control error signal is generated to control the rotation system. (Note) The signal read from the optical digital audio disk becomes asynchronous data due to disk eccentricity, motor rotation speed changes, etc. An example of an asynchronous data write/read circuit in such a rotating system is a first-in/first-out memory (FIFO First-in-First-out memory).
There are memory circuits called "Out" and memory circuits having the following configurations. This will be explained in FIG. 1 is a write address counter to which the write address clock Wa is input; 2 is a read address counter to which the read address clock Ra is input; 3 is an address selector;
The address at which the No. 4 instruction (write, read) is executed is specified by the write address counter 1 and the read address counter 2. 5 is an input buffer circuit. The address selector 3, RAM 4, and input buffer circuit 5 operate in synchronization with the write signal Wr,
Data is sequentially written to designated addresses in RAM 4 through input buffer circuit 5. On the other hand, the input data written to the designated address of the RAM 4 is sequentially outputted from the latch circuit 6 in synchronization with the latch signal Rr. [Problems that the invention attempts to solve] The former FIFO memory has a small storage capacity, and
In the latter case, when a write operation and a read operation match, one of the write address clock Wa and read address clock Ra must be controlled, or the command must be invalidated, and the circuit configuration for this is complicated. become. [Means for solving the problem] The present invention forms a latch signal Rr after a predetermined time T has elapsed from the read address clock Ra when the write signal Wr and the read address clock Ra do not overlap. If the read address clock Ra and write signal Wr overlap,
The above problem is solved by forming the latch signal Rr after a predetermined time T has elapsed after the end of the write signal Wr. The flip-flop circuit 11 is set as follows. (b) An AND circuit 12 to which the output of the flip-flop circuit 11 and the write signal Wr are input. (c) A counter having an initial value preset by a presetting means, counting clock signals from the initial value, outputting a carry signal at a full count, and resetting the flip-flop circuit 11 using the carry signal. , the counter 7 becomes capable of counting clock signals from the initial value by the output of the AND circuit 12. (d) Means for generating a latch signal Rr when the counter 7 reaches a predetermined value. It is characterized by comprising the following. [Operation] To explain only the operation of the characteristic part of the present invention, when the write signal Wr and the read address clock Ra overlap, the flip-flop circuit is set by the read address clock Ra, and the flip-flop circuit is set. The output Q becomes [H], but the write signal Wr maintains the [L] state. Therefore, the counter stops its counter operation and remains on standby in its initial state. When the write signal Wr ends and becomes [H], the AND output of this [H] and the above output Q [H] becomes [H], and thereby the counter becomes ready to count from the initial value. Clock signals are counted sequentially. When the counter reaches the predetermined count value,
That is, the latch signal Rr is generated and output after a predetermined time (T) has elapsed after the write signal Wr ends. [Example] This will be explained with reference to FIG. In the figure, parts equivalent to those of the conventional example shown in FIG. 3 are given the same reference numerals, and their explanations will be omitted. 7 is a preset counter for determining a predetermined time T, which includes a clock input terminal 7a to which a clock signal CK is input, and an enable and load terminal 7.
b. Preset means 8 is provided for setting an initial value for starting the counter. The preset means 8 can be realized by grounding each preset terminal or by applying a predetermined voltage.
Further, the counter 7 is brought into a state in which it can count from the initial value by an enable load signal (described later). The counter 7 counts the clock signal CK from the preset initial value A0 [AnAn-1...A2A1], and outputs the carry signal Ca when it reaches the full count value Af [1 1 1... 1 1]. . In addition, among the outputs Q [QnQn-1 ... Q2Q1] of the counter 7, only the LSB (Least Significant Bit) output [Q1] is passed through the inverter circuit 9 to the first AND.
Input to circuit 10 and use the AND output as a latch signal
Extract as Rr. 11 is an RS flip-flop circuit, a read address clock Ra is input to a set terminal 11s, an output Q thereof is input to one input terminal of a second AND circuit 12, and a write signal Wr is input to the other input terminal. Ru. And AND of both signals
The output is input to the enable and load terminal 7b of the counter 7 as an enable load signal. This puts the counter 7 in a state where it can count from the initial value. Furthermore, the carry signal Ca is input to the reset terminal 11r of the RS flip-flop circuit 11 at the time when the counter 7 reaches the full count value Af, and is reset. The operation of the above embodiment will be explained below with reference to the time chart of FIG. (1) When the write signal Wr and the read address clock Ra do not overlap In this state, the write signal Wr is [H] and the RAM 4 is in the read state. The RS flip-flop circuit 11 is set by the read address clock Ra input to the set terminal 11s, and the AND output [H] of its output Q [H] and the write signal Wr [H] is used to enable and load the counter 7. It is input to terminal 7b. As a result, the counter 7 becomes ready to count from the initial value A0, and the clock signal CK is successively counted. Counter 7 is one value before the full count value Af - 1 [1 1 1 ... 1 0], and LSB [Q1] (

A latch signal Rr is output as an AND output of each bit of the inverted value [1 1 1 . . . 1 1]. When the counter 7 reaches the full count value Af, a carry signal Ca is output, thereby resetting the RS flip-flop circuit 11 and returning to its original state. (2) When the write signal Wr and the read address clock Ra overlap In this state, the write signal Wr is [L] and the RAM 4 is in the write state. The RS flip-flop circuit 11 is set by the read address clock Ra, and its output Q
However, the write signal Wr remains in the [L] state. Therefore, the counter 7 stops its counting operation and remains on standby in its initial state. When the write signal Wr ends and becomes [H], this [H] and the above output Q [H] are AND output [H]
is the enable and load terminal 7b of the counter 7
is input. As a result, the counter 7 becomes capable of counting from the initial value A0, and the clock signal CK is successively counted. Hereinafter, in the same way as in (1), the latch signal Rr is activated after a predetermined time (T) has passed after the write signal Wr ends.
is formed and output. During the above predetermined time (T), the counter 7 has an initial value of A0.
The predetermined time (T) can be changed in proportion to the number of counts counted from Af-1 by arbitrarily presetting the initial value A0. [Effect of the invention] With the above configuration, (a) write signal Wr
If not, a latch signal Rr is formed after a predetermined time (T) has elapsed from the read address clock Ra,
When the read address clock Ra and the write signal Wr overlap, the latch signal Rr can be formed after a predetermined time (T) has elapsed after the write signal Wr ends. ,
Either the write address clock Wa or the read address clock Ra should be controlled.
Or, there is no need for a circuit to invalidate the command,
(c) A circuit using a large capacity RAM can be realized simply and inexpensively.
There are effects such as

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of an asynchronous data write/read circuit according to the present invention, FIG. 2 is a time chart showing its operation, and FIG. 3 is a diagram showing the configuration of a conventional asynchronous data write/read circuit. 1... Address counter for writing, 2... Address counter for reading, 3... Address selector, 4... Random access memory, 5... Input buffer circuit, 6... Latch circuit, 7... Counter, 8... Preset means, 9... Inverter circuit, 10... First AND circuit, 11... RS flip-flop circuit, 12... Second AND circuit.

Claims (1)

[Claims for Utility Model Registration] A write address counter 1 to which the write address clock Wa is input, a read address counter 2 to which the read address clock Ra is input, the write address counter 1 and the read address. It consists of an address selector 3 that selects the address at which writing and reading are to be performed in the random access memory 4 based on the output of the counter 2, and a random access memory 4. In the configuration in which the input data written to the specified address is sequentially written to the specified address in step 4 and read out sequentially in synchronization with the latch signal Rr, the following configuration requirements (a) to (d) are satisfied. A flip-flop circuit 11 is set by the read address clock Ra. (b) An AND circuit 12 to which the output of the flip-flop circuit 11 and the write signal Wr are input. (c) A counter having an initial value preset by a presetting means, counting clock signals from the initial value, outputting a carry signal at a full count, and resetting the flip-flop circuit 11 using the carry signal. , the counter 7 becomes capable of counting clock signals from the initial value by the output of the AND circuit 12. (d) Means for generating a latch signal Rr when the counter 7 reaches a predetermined value. An asynchronous data write/read circuit comprising: