JPH0241763B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to a magnetic disk control device used for transferring data between a CPU and a magnetic disk device as an external storage device.

``Prior Art'' Normally, data processed by a CPU (central processing unit) and data processed by a magnetic disk device have different data formats. for example
While the CPU processes parallel data,
Data read and written by a magnetic disk device is usually serial data. Furthermore, check bits for error detection are often added to data written to magnetic disk drives. Furthermore, the data processing speeds of a CPU and a magnetic disk device are usually different. For this reason, a magnetic disk control device is used as a device for transferring data between the two devices.

FIG. 1 shows the general configuration of a conventionally used magnetic disk control device. Byte parallel data D1 created by CPU
is stored in the buffer circuit 11. The serial circuit 12 converts the data D2 output from the buffer circuit 11 into bit-serial data D3.

This data D3 is input to the first and second selection circuits 13 and 14. First selection circuit 13
is adapted to input data D4 read from the magnetic disk device 15 and the above-mentioned data D3. When writing to the magnetic disk device 15, data D3 is selected by the read/write control signal 17 supplied from the timing generation circuit 16 and sent to the CRC generation circuit 18.

Incidentally, the data D1 is also supplied to the counter circuit 19. The counter circuit 19 starts counting operation at the stage when the supply of a batch of data to be written to the magnetic disk device 15 is started. A count value signal 21 representing a count value is decoded by a decoder 22, and a CRC generation circuit control signal 23 and a selection circuit control signal 24 are generated.

CRC generation circuit control signal 23 is CRC generation circuit 1
8, and data D5 with check bits added thereto is created. Data D5 is supplied to the second selection circuit 14. Selection circuit control signal 24
is supplied to the second selection circuit 14 and used for control for separating data D3 and data D5. Data D output from the second selection circuit 14
6 is written to the magnetic disk device 15.

On the other hand, data D4 read from the magnetic disk device 15 is supplied to the serial circuit 12, where it is converted into byte-parallel data D7. The synchronization detection circuit 26 detects when the data D7 constitutes a synchronization mark, and outputs the mark detection signal 2.
7 is supplied to the timing generation circuit 16. At the same time, the timing generation circuit 16 starts controlling each section and starts information transfer to the CPU. That is, data D7 is temporarily stored in the buffer circuit 28 and then sent to the CPU as data D8. The data D4, which is the basis of the data D8 sent out in this way, passes through the first selection circuit 13 and then passes through the CRC
The signal is supplied to the generating circuit 18, where it is checked for errors.

Because the data transfer speeds differ between the CPU and the magnetic disk device, conventional magnetic disk control devices are provided with a counter circuit 19 and a decoder 22 to check bits for a predetermined length of data D1. I was synchronizing the timing of the additions. These circuits include circuit parts for setting count values and decode values, and have the disadvantage that the magnetic disk control device itself becomes expensive because it uses many logic elements and the like. In addition, the magnetic disk control device itself is not versatile;
When connecting a magnetic disk device with new specifications to the CPU, there was also the problem that the magnetic disk control device had to be redesigned.

OBJECTS OF THE INVENTION In view of the above circumstances, it is an object of the present invention to provide a magnetic disk control device that is simplified and can be easily adapted to new magnetic disk devices.

``Structure of the Invention'' The present invention includes a storage means for temporarily storing a control signal (timing signal) for adding check bits output from a central processing unit controlled by a microprogram, and a storage means for temporarily storing the control signal (timing signal) for adding a check bit, and the storage result as described above. A FIFO memory for writing in synchronization with storage data also output from the central processing unit, a reading means for reading out the data and control signals written to the FIFO memory in synchronization with the operating clock of the magnetic disk device, and The magnetic disk control device is provided with a check bit adding means for adding check bits to data using the received control signal.

Then, using the check bit addition control signal, data with check bits added is created without the need for a counter or decoder, and this data is written to an external storage device in synchronization with the operating clock of the magnetic disk device. .

"Example" The present invention will be explained in detail with reference to Examples below.

FIG. 2 shows the magnetic disk control device of this embodiment. Components that are the same as those in FIG. 1 are given the same reference numerals, and explanations of those components will be omitted.

By the way, the CPU is generally controlled by a microprogram. From the CPU, byte-parallel variable length data D1 (D _o ~
D ₀ ) and a control signal D1 for adding check bits.
1 is supplied to this magnetic disk controller. Of these, the latter control signal D11 is a parallel 2-bit signal, one of which represents a section of variable length data D1. Moreover, the other signal represents the timing for adding CRC. These control signals D11 are supplied to the first latch circuit 31.

The first latch circuit 31 is composed of, for example, two D flip-flops arranged in parallel, and each latches parallel 2-bit control data D11. The latch output 34 of the first latch circuit 31 is a parallel 2-bit signal,
The latch output 34A (FIG. 3b) representing the section of the variable length data D1 described above and the latch output 34B representing the timing for adding CRC are byte-parallel data D1 (D _o to D in FIG. 3A). _D0 )
It is also supplied to the buffer circuit 33.

The control signal D11 is once latched by the latch circuit 31 and then output as the latch output 34 to the buffer circuit 3.
The reason why we decided to supply the data to the control signal D11 is to correct the time axis deviation between the data D1 and the control signal D11 created in different parts of the CPU on the input side of the buffer circuit 33, so that the timing of both can be accurately adjusted. This is to make them match. The buffer circuit 33 is constituted by a FIFO (FIRST IN FIRST OUT) memory that inputs the data D1 and the latch output 34 simultaneously in parallel.

The buffer circuit 33 outputs data D2 (FIG. 3d) and two types of control signals 35A and 35B (FIG. 3e and f) in synchronization with the data writing speed to the magnetic disk device 15. These parallel 2-bit control signals 35A and 35B are the timing control signal 3 output from the timing generation circuit 16.
7 into the second latch circuit 38.

The second latch circuit 38 is also the same as the first latch circuit 31.
It has the same circuit configuration as . Buffer circuit 33
Two types of control signals 35A and 35B output from
It was decided to latch the buffer circuit 33.
This is to correct the deviation on the time axis between the signals outputted through independent circuits within the circuit, so that their timings completely match. Therefore, the timing at which data D2 is input to the serial circuit 12 and the two types of control signals 35A, 35
The timing at which B is latched by the latch circuit 38 will be exactly the same.

The data D2 supplied to the serial circuit 12 is
It is converted into serial data D3 (Fig. 3g). FIG. 3h shows the data after this serial conversion, and FIG. 3i shows the details of the data D3 after this serial conversion.

The second latch circuit 38 outputs the CRC generation circuit control signal 23 whose timing accurately matches the serial data D3 as a latch output of the control signal 35.
(Fig. 3k) and selection circuit control signal 24 (Fig. 3k)
Figure j) is output respectively. By these
The CRC generation circuit 18 and the second selection circuit 14 are controlled, and data D6 (FIG. 3l) is written to the magnetic disk device 15.

The circuit operation for reading data from the magnetic disk device 15 is similar to the conventional example shown in FIG.

"Effects of the Invention" As explained above, according to the present invention, the central processing unit, which knows in advance the amount of data to be stored in a predetermined sector of a magnetic disk device, can determine the relationship between that amount and the remaining capacity of the sector. The rate at which check bits are added is determined by the check bits, and this is output as a control signal representing the timing for adding check bits.Since the check bits are added, it is necessary to enable the corresponding sector in relation to the storage capacity that can be allocated to the check bits. It can be used to maximize the reliability of data checks. Of course, it is also possible for conventional magnetic disk controllers to receive notification from the central processing unit of the amount of data to be stored in a predetermined sector, calculate the capacity that can be allocated to check bits, and add check bits accordingly. be. However, for this purpose, it is necessary to arrange an arithmetic circuit and the like on the magnetic disk control device side, which makes the device complicated and expensive. In this sense, the present invention has the effect that the device can be manufactured easily and at low cost.

In addition, in the present invention, a
Since the control signal for adding check bits to the FIFO memory is written in synchronization with the data for storage, the counter circuit and decoder that were conventionally required are no longer required, simplifying the device.

Furthermore, in the present invention, since the central processing unit can freely set the length of data to which check bits are added, control can be performed in units of words or bytes. Therefore, even if a magnetic disk device is to be replaced with a superior device with better performance, this can be done simply by changing the microprogram, and there is no need to change the hardware. In other words, it is possible to construct a flexible and versatile magnetic disk control device.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a conventional magnetic disk control device, Fig. 2 is a block diagram of a magnetic disk control device in an embodiment of the present invention, and Fig. 3 explains the operation of the magnetic disk control device in this embodiment. FIG. 15...Magnetic disk device, 18...CRC generation circuit (check bit adding means), 31...first latch circuit, 33...buffer circuit (FIFO
memory).

Claims (1)

[Scope of Claims] 1. Storage means for temporarily storing a check bit addition control signal output from a central processing unit controlled by a microprogram; Write in synchronization with storage data
A FIFO memory, a reading means for reading data and control signals written in the FIFO memory in synchronization with an operating clock of a magnetic disk device, and a check bit adding means for adding check bits to data using the read control signals. A magnetic disk control device, comprising: storing data to which a check bit has been added in the magnetic disk device.