JPH0332823B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for controlling access to a memory device in an information processing system or the like.

As is well known, a master/slave type flip-flop usually consists of a two-stage flip-flop built into one integrated circuit, with the front-stage flip-flop configured to be set by an external input signal, and the rear-stage flip-flop configured to be set by an input signal from the outside. is set by the output of the flip-flop at the front stage only when specified from the outside, and is configured to maintain that state.

Therefore, in certain limited applications, it is possible to use the registers constructed by the flip-flops in both stages as registers that can hold different contents. It may be possible to reduce the number of required parts.

The two registers configured in this manner can also be used as a buffer for data and instructions input/output to the memory device.

[Problems to be solved by conventional technology and invention]

FIG. 2 is a block diagram showing an example of the structure of a memory access control circuit that uses a register constituted by a master/slave type flip-flop circuit to hold information to be input/output to a memory device.

The memory device 1 has a function of outputting information at a storage address specified by an address line 2 to a read information line 3 or writing information from a write information line 4 to a specified storage address using a known control method. have.

The storage address is specified from either the data address register 5 that holds the address of data to be input/output to the memory device 1, or the instruction address register 6 that holds the storage address for reading instructions.

In the memory device 1, one word of information stored at one storage address consists of fixed-length data or instructions (for example, 32 bits) and a redundant code of, for example, 5 bits that constitutes an error correction code in combination with the data or instruction.
The read information line 3 and the write information line 4 have the same configuration and one word width.

The information read from the memory device 1 is stored in a master register 8 constituted by a flip-flop on the master side of the master/slave type flip-flop circuit 7.
is entered and retained.

If this access is for reading an instruction, the control line 11 from the instruction buffer control circuit 10
The output of the master register 8 is set in the slave register 9 by the next clock signal.

The slave register 9 is a register constituted by a flip-flop on the slave side of the master/slave type flip-flop circuit 7.

The instruction buffer control circuit 10 usually always reads out one step of the instruction and holds it in the slave register 9. When the execution of one instruction is finished, if the next instruction is in the slave register 9, the output is sent to the error detection and correction circuit. (hereinafter referred to as the ECC circuit) 12.

The ECC circuit 12 has a function of checking information read from the memory device 1 based on an error correction code, a function of executing error correction when a correctable error is detected as a result, and a function of performing error correction on the memory device 1.
It has a function of generating a redundant code for configuring an error correction code for data written to.

In this case, the ECC circuit 12 performs error detection/correction processing on the instruction, and the output instruction is set in the instruction instruction register 13.
The contents of are used for instruction execution in the usual manner.

When the instruction held in the slave register 9 is transferred to the instruction register 13, the instruction buffer control circuit 1
0 reads the next instruction to the slave register 9 at an appropriate timing as described above.

When accessing data stored in the memory device 1 by executing a command or the like, the memory device 1
The data read from is held in the master register 8 in the same manner as described above. In the case of data, the output of the master register 8 is input to the ECC circuit 12,
Error detection/correction processing is performed in the same manner as described above, and the output thereof is sent to an arithmetic circuit or the like via a data line 14.

When writing data to the memory device 1, data to be written is received from an arithmetic circuit or the like via a data line 15. When writing an entire word, the data on the data line 15 is held in the master register 8 via the gate circuit 19, and the output of the master register 8 is
input to the ECC circuit 12 to obtain a redundant code output 17;
This redundant code 17 and the contents of the data portion held in the master register 8 are connected to write information line 4.
By placing it on the , it is stored at the specified storage address.

In the case of so-called partial writing, in which only a part of one word of data is updated and the other part preserves the previous memory contents, one of the memory addresses to be written is
The word is first read from the memory device 1 and held in the master register 8, and a part of it is updated before being rewritten.

The data read for this purpose is input from the master register 8 to the ECC circuit 12 in the same manner as described above.
Error detection processing is performed, and if there is no error, the error detection processing is completed and only the specified portion in the master register 8 is updated with data from the data line 15.

Thereafter, the data in the master register 8 and the redundant code generated by the ECC circuit 12 for the data are written into the memory device 1 in the same manner as in the write operation.

ECC is applied to data read from memory device 1 to master register 8 for partial writing.
If a correctable error is detected in the circuit 12, it is necessary to correct the contents of the master register 8 to correct data and then perform the above-described partial write process.

However, if the output of the ECC circuit 12 is left in the correction processing state and the master register 8 is directly changed, the input of the ECC circuit 12 will be changed by itself, making the correction output unstable.

For this purpose, for example, the correction output 18 of the ECC circuit 12 is once set to the buffer 16, and
The master register 8 is modified by setting the output of the master register 8 to the master register 8.

As described above, even if a master/slave type flip-flop is used, there is a problem that the effect of reducing the number of components is diminished because the buffer 16 must be provided.

[Means for solving problems]

The above-mentioned problem is that the master/slave type flip-flop circuit has a master register constituted by a master-side flip-flop and a slave register constituted by a slave-side flip-flop, and the data input/output to the memory device is transferred to the master register. The instructions read from the memory device are held in the slave register, and when a part of the data held in the master register is changed and rewritten to the memory device, the instructions read from the memory device and the instructions read from the memory device are changed. If an error is detected in the data held in the master register by error correction code inspection, the data is transferred to the slave register and error correction processing using the error correction code is executed for the data in the slave register. This problem is solved by the memory access control method of the present invention.

[Effect]

In other words, when an error is detected in the data of the master register and needs to be corrected, the contents of the master register are transferred to the slave register, the output of the slave register is input to the ECC circuit for correction processing, and the output is used to correct the master register. Fix it.

Therefore, the correction processing input of the ECC circuit does not change due to modification of the master register, a stable correction output can be obtained, and the number of components is reduced.

Note that when the correction process is performed as described above, the instruction buffer control circuit thereafter controls the next instruction to be read out from the memory device again and held in the slave register.

〔Example〕

FIG. 1 is a block diagram showing one embodiment of the present invention. In the figure, the same parts as in FIG. 2 are designated by the same reference numerals.

As in the prior art, master register 8 is used as a register to hold data to be input/output to memory device 1, and slave register 9 is used as an instruction buffer to hold the next instruction to be executed.

As described above, the data read into the master register 8 for partial writing is checked for errors by the ECC circuit 12.

If no error is detected, partial writing is processed in the same way as in the conventional example.

If a correctable error is detected, ECC
Circuit 12 controls master/slave flip-flop 7 via control line 20 to transfer the contents of master register 8 to slave register 9;
Switch the input to the ECC circuit 12 to the slave register 9 side.

Further, the signal on the control line 20 is also sent to the instruction buffer control circuit 10, and the instruction buffer control circuit 10 knows that the instruction held in the slave register 9 has been destroyed, so it can issue the next instruction after that, for example. At the start of the control set in register 13,
Control is performed to read the next instruction from the memory device 1 again.

The ECC circuit 12 continues error correction processing following error detection on the input from the slave register 9, and sets the correction data to the master register 8 via the data line 18, so that the ECC circuit 12 completes the correction processing. do.

Next, part of the data in the master register 8 is updated using the data on the data line 15.

The ECC circuit 12 switches to a redundant code generation state, takes the data of the master register 8 as input, and outputs a redundant code output 17.

The redundant code output 17 and the data in the master register 8 are combined and rewritten into the memory device 1 via the write information line 4, thereby completing the partial write process.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, the buffer required for memory access control is reduced, so there is a significant industrial effect of improving the economic efficiency and reliability of the information processing system.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional configuration. In the figure, 1 is a memory device, 5 is a data address register, 6 is an instruction address register, 7 is a master/slave type flip-flop circuit, 8 is a master register, 9 is a slave register, 10 is an instruction buffer control circuit, and 12 is an ECC circuit. , 13
1 is an instruction register, 16 is a data buffer, and 20 is a control line.

Claims (1)

[Claims] 1 A master/slave type flip-flop circuit has a master register constituted by a master-side flip-flop and a slave register constituted by a slave-side flip-flop. An instruction read from the memory device is held in the slave register, and when a part of the data held in the master register is changed and rewritten to the memory device, the instruction is read from the memory device and held in the master register. If an error is detected in the data by error correction code checking,
A memory access control system characterized in that the data is transferred to the slave register, and the data in the slave register is subjected to error correction processing using an error correction code.