JPH0241767B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a digital proportional-integral circuit that obtains an output digital signal by adding proportional-integral characteristics to a binary input digital signal.

Configuration of Conventional Example and Its Problems FIG. 1 is an electrical connection diagram showing a conventional example of an analog proportional-integral circuit, and FIG. 2 is a waveform diagram for explaining its operation.

The components of the analog proportional-integral circuit are an operational amplifier 1, an input resistor 2, a feedback capacitor 3, and a feedback resistor 4. Now, when a potential difference occurs between the input voltages E ₁ and E ₂ , a current flows through the input resistor 2, and the feedback capacitor 3 is charged with charge, causing the output voltage E ₀ to change.
As shown in Figure 2, the output voltage E ₀ decreases when E ₁ > E ₂ (~t ₁ , t ₄ ~ _{t 5} ), and stops when E ₁ = E ₂ (t ₁ ~ t 5 ). _t2 , _t3 to _t4 , _t5
), and when E ₁ <E ₂ , the potential increases (t ₂ to _{t 3} ). The transfer function G _(s) of this circuit is G _(s) = 1 + sT ₂ /sT1 (1). However, T ₁ = CR ₁ , T ₂ = CR ₂ , C is the capacitance value of feedback capacitor 3, R ₁ is the resistance value of input resistor 2, R ₂ is the resistance value of feedback resistor 4, and s is the Laplace operator. .

When formula (1) is expanded, G _(s) = 1/sT1+T ₂ /T ₁ ...(2). That is, it has proportional-integral characteristics of integral and proportional. Note that the magnitude of the current flowing through the input resistor 2 is proportional to the potential difference between the input voltages E ₁ and E ₂ , so
The charging and discharging of the charge in the feedback capacitor 3 is integrated proportionally to the potential difference. However, the output voltage E ₀ shown in FIG.
The slope of the potential changes in proportion to the potential difference between E ₁ and E ₂ .

When converting such a proportional-integral circuit into an integrated circuit (iC), three input/output pins and external CR components are required, which hinders the reduction of external components and the number of pins by converting into an iC. Ta. In addition, it was susceptible to variations in CR components, changes in power supply voltage, changes in temperature, changes over time, etc. Furthermore, if it is desired to switch the frequency characteristics to multiple modes using a mode command signal, there are problems such as the need for more external components.

Purpose of the Invention The present invention solves the above-mentioned conventional problems.
The present invention provides a digital proportional-integral circuit in which all components are digitalized and frequency characteristics can be switched by a mode command signal.

Structure of the Invention The present invention includes gate means for inhibiting clock pulses when an input digital signal is at a predetermined value, at least one most significant bit of the input digital signal as an up-down signal input, and an output of the gate means as a clock input. an up-down counter, variable multiplication means for switching a coefficient by which the input digital signal is multiplied by a mode command signal, and addition or subtraction means for adding or subtracting the output of the up-down counter and the output of the variable multiplication means. This is a digital proportional-integral circuit that obtains an output digital signal corresponding to the mode command signal from the addition or subtraction means, and digitizes all the components and uses the mode command signal to control the gain in the high frequency region, that is, the frequency characteristic. It is possible to switch. Further, the present invention is configured to use proportional frequency dividing means in place of the gate means, and the proportional frequency dividing means divides the frequency of the clock pulse into a frequency proportional to the absolute value of the difference between the input digital signal and a predetermined value. If this output is used as a clock for an up-down counter, the performance of the proportional-integral circuit can be improved.

DESCRIPTION OF THE EMBODIMENTS FIG. 3 is a block diagram showing one embodiment of the present invention, FIG. 4 is its operating waveform diagram, and FIG. 5 is a frequency characteristic curve showing proportional-integral characteristics.

In FIG. 3, 5 is a gate means, 6 is an up-down counter, 7 is a variable multiplication means, 8 is an addition means, _D1 is a binary input digital signal,
_D2 is the output of the up-down counter, _D3 is the output of the variable multiplier, _D4 is the output digital signal, S1
is the clock pulse, and S2 is the output from the gate output stage.

The gate means 5 outputs a clock pulse S when the input digital signal D ₁ is equal to a predetermined value D ₀ (D ₁ =D ₀ ).
The configuration is such that the output of 1 is prohibited and is output when they are not equal (D ₁ ≠D ₀ ), and the gate output S2 is used as the clock input of the up-down counter 6. On the other hand, the up-down counter 6 receives the input digital signal _D1.
At least one bit of the most significant bit is inputted as an up-down signal to count up or down the gate output S2. Then, an integrated output signal _D2 is obtained from the up-down counter 6. Also,
The input digital signal _D1 is input to the variable multiplier 7 and multiplied by a coefficient K depending on the mode command signal. Then, in the adding means 8, the output _D2 of the up-down counter 6 and the output _D3 of the variable multiplication means 7 are added, and the added output _D4 is obtained as an output digital signal.

To explain the operation of FIG. 3 with reference to FIG. 4, the operation of the up-down counter ₆ is switched between up and down (or down and up) depending on whether the input digital signal D1 is larger or smaller than a predetermined value _D0 . . That is, the output D ₂ has a relationship between D ₁ and D ₀ such that D ₁ > D ₀ (or
When D ₁ < D ₀ ), up count (t ₂ to _{t 3} ), D ₁ =
Counting stops when D ₀ (t ₁ ~ t ₂ , t ₃ ~ t ₄ , t ₅ ~),
It is configured to count down (~ _t1 , _t4 ~ _t5 ) when _D1 < _D0 (or _D1 > _D0 ).

Here, to detect whether D ₁ >D ₀ or D ₁ <D ₀ , it is sufficient to use at least one most significant bit of the input digital signal D ₁ . That is, the input digital signal
When D ₁ is 6 bits and the predetermined value D ₀ is 100000 (this means that the most significant bit is 1 and the lower bits are all 0)
For example, if the most significant bit of D ₁ is 1, D ₁ >D ₀ , and if it is 0, D ₁ <D ₀ , it is possible to easily detect whether the value is large or small. In this case, similar detection is possible even if the predetermined value D ₀ is set to 011111.

In the above example, input digital signal with predetermined value D ₀
D is set to 1/2 of ₁ , but 1/4, 3/4
It is also possible to set the value to a value of . In this case, the most significant two bits may be used as an up-down signal, and a logic circuit (decoder) for detection is required.

On the other hand, in the gate means 5, the input digital signal
D ₁ is decoded, and when D ₁ =D ₀ , an inhibition signal is obtained and gate output of clock pulse S1 is inhibited.

Here, the time constant T ₁ in equation (2) can be obtained as T ₁ =1/ _ck (3). However, _ck is the frequency of the clock pulse input to the up-down counter 6.

If the output D ₂ of the integrating circuit consisting of the gate means 5 and the up-down counter 6 and the output D ₃ of the variable multiplication means 7, which is the input digital signal D ₁ multiplied by the coefficient K, are added in the addition means 8, then equation (2) is obtained. proportional element of
T ₂ /T ₁ can be added. That is, T ₂ /T ₁ =K (4).

With the above, the proportional-integral circuit can be fully digitalized, and if the coefficient K of the variable multiplier 7 is switched according to the mode command signal to K ₁ , K ₂ , K ₃ . . .
As shown in FIG. 5, the gain in the high frequency region of the proportional-integral circuit, which is the object of the present invention, ie, the frequency characteristics can be changed. Here, from equation (4), T ₂ =
Since K·T ₁ , T ₂ changes in proportion to the coefficient K, and as a result, the corner frequency ₂ determined by T ₂ switches to _2a , _2b , _2c, etc., as shown in FIG.

Note that the operation of the up-down counter 6 is expressed as D ₁
If the configuration is such that the count is down when >D ₀ and the count is up when D ₁ <D ₀ , the adding means 8 is used as a subtracting means so that the output digital signal D ₄ with respect to the input digital signal D ₁ has negative polarity. be able to.

Next, FIG. 6 is a block diagram showing a second embodiment of the present invention, which differs from the embodiment in FIG.
Proportional frequency dividing means 9 replaces gate means 5 in FIG.
The point is that we used D ₀ is a predetermined value, and S3 is the output of the proportional frequency dividing means 9. The proportional frequency dividing means 9 inputs the clock pulse S1 and divides it into a digital signal _D1 and a predetermined value.
D Divide into a frequency proportional to the absolute value of the difference from ₀ ,
The frequency-divided output S3 is used as the clock input of the up-down counter 6. This allows up-counting and down-counting in proportion to the absolute value |D ₁ −D ₀ | of the difference between the input digital signal D ₁ and the predetermined value D ₀ . This is a digital implementation of the conventional example shown in FIG. 1 in which the feedback capacitor is charged and discharged in proportion to the input potential difference. Here, the clock frequency _ck in equation (3) is the proportional frequency dividing means 9.
The lowest frequency of the output S3, that is, |D ₁ −D ₀ |=1
This is the frequency when .

The up-down counter 6 of the first and second embodiments described above decodes the count output D ₂ and outputs D ₂
The input of clocks S2 and S3, which are input when is the maximum value and minimum value, is prohibited, and when the maximum value is detected, the clock input is prohibited with the next down command, and when the minimum value is detected, with the next up command. Add a function to cancel. Thereby, overflow and underflow of the up-down counter 6 can be prevented.

Effects of the Invention As is clear from the above explanation, all the components are digitalized, and the gain in the high frequency region of the proportional-integral circuit, that is, the frequency characteristic, can be switched according to the mode command signal, and it is suitable for iC implementation. Its practical effects are great.

[Brief explanation of the drawing]

FIG. 1 is an electrical connection diagram showing the conventional configuration of an analog proportional-integral circuit, FIG. 2 is its operating waveform diagram, FIG. 3 is a block diagram of an embodiment of the digital proportional-integral circuit of the present invention, and FIG. 5 is a diagram of its operating waveforms, FIG. 5 is a diagram of its frequency characteristic curve, and FIG. 6 is a block diagram of another embodiment of the present invention. 5... Gate means, 6... Up-down counter, 7... Variable multiplication means, 8... Addition or subtraction means, 9... Proportional frequency division means.

Claims (1)

[Scope of Claims] 1. Gate means for inhibiting clock pulses when the input digital signal is at a predetermined value, at least one most significant bit of the input digital signal is used as an up-down signal input, and the output of the gate means is used as a clock input. an up-down counter; variable multiplication means for switching a coefficient by which the input digital signal is multiplied by a mode command signal; and addition or subtraction means for adding or subtracting the output of the up-down counter and the output of the variable multiplication means. A digital proportional-integral circuit, wherein an output digital signal corresponding to the mode command signal is obtained from the addition or subtraction means. 2. Proportional frequency dividing means for dividing the clock pulse into a frequency proportional to the absolute value of the difference between the input digital signal and a predetermined value; and at least one most significant bit of the input digital signal as an up-down signal input; an up-down counter whose clock input is the output of the up-down counter; a variable multiplication means which switches a coefficient by which the input digital signal is multiplied by a mode command signal; and an output from the up-down counter and an output from the variable multiplication means. 1. A digital proportional-integral circuit comprising: addition or subtraction means, wherein an output digital signal corresponding to the mode command signal is obtained from the addition or subtraction means.