JPH0241768B2 - - Google Patents

Info

Publication number
JPH0241768B2
JPH0241768B2 JP59071977A JP7197784A JPH0241768B2 JP H0241768 B2 JPH0241768 B2 JP H0241768B2 JP 59071977 A JP59071977 A JP 59071977A JP 7197784 A JP7197784 A JP 7197784A JP H0241768 B2 JPH0241768 B2 JP H0241768B2
Authority
JP
Japan
Prior art keywords
output
input
proportional
digital signal
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59071977A
Other languages
Japanese (ja)
Other versions
JPS60215242A (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP59071977A priority Critical patent/JPS60215242A/en
Publication of JPS60215242A publication Critical patent/JPS60215242A/en
Publication of JPH0241768B2 publication Critical patent/JPH0241768B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/64—Digital differential analysers, i.e. computing devices for differentiation, integration or solving differential or integral equations, using pulses representing increments; Other incremental computing devices for solving difference equations

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Mathematical Physics (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Feedback Control In General (AREA)

Description

【発明の詳細な説明】 産業上の利用分野 本発明は２進数の入力デイジタル信号に比例積
分特性を付加した出力デイジタル信号を得るデイ
ジタル式比例積分回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a digital proportional-integral circuit that obtains an output digital signal by adding proportional-integral characteristics to a binary input digital signal.

従来例の構成とその問題点 第１図はアナログ式比例積分回路の従来例を示
す電気的結線図、第２図はその動作説明に供する
波形図で、第３図はその周波数特性を示す曲線図
である。Configuration of conventional example and its problems Figure 1 is an electrical wiring diagram showing a conventional example of an analog proportional-integral circuit, Figure 2 is a waveform diagram to explain its operation, and Figure 3 is a curve showing its frequency characteristics. It is a diagram.

アナログ式比例積分回路の構成要素は、オペア
ンプ１、入力抵抗２、帰還コンデンサ３、帰還抵
抗４である。今、入力電圧E1，E2に電位差が生
じると入力抵抗２に電流が流れ、帰還コンデンサ
３に電荷が充電されて出力電圧E0が変化する。
出力電圧E0は第２図に示すように、E1＞E2のと
き電位が下降（〜t1、t4〜t5）し、E1＝E2のとき
電位が停止（t1〜t2、t5〜）し、E1＜E2のとき電
位が上昇（t2〜t3）する動作をする。この回路の
伝達関数G(s)は、 G(s)＝１＋sT2／sT1 ……(1) となる。但し、T1＝CR1、T2＝CR2、Ｃは帰還
コンデンサ３の容量値、R1は入力抵抗２の抵抗
値、R2は帰還抵抗４の抵抗値、Ｓはラプラス演
算子である。 The components of the analog proportional-integral circuit are an operational amplifier 1, an input resistor 2, a feedback capacitor 3, and a feedback resistor 4. Now, when a potential difference occurs between the input voltages E 1 and E 2 , a current flows through the input resistor 2, charges are charged in the feedback capacitor 3, and the output voltage E 0 changes.
As shown in Figure 2, the output voltage E 0 decreases when E 1 > E 2 (~t 1 , t 4 ~ t 5 ), and stops when E 1 = E 2 (t 1 ~ t 5 ). t2 , t5 ~), and when E1 < E2 , the potential increases ( t2 ~ t3 ). The transfer function G (s) of this circuit is G (s) = 1 + sT 2 /sT 1 (1). However, T 1 = CR 1 , T 2 = CR 2 , C is the capacitance value of feedback capacitor 3, R 1 is the resistance value of input resistor 2, R 2 is the resistance value of feedback resistor 4, and S is the Laplace operator. .

(1)式を展開すると、 G(s)＝１／sT1＋T2／T1 ……(2) となる。即ち、積分と比例の比例積分特性を有し
ている。なお、入力抵抗２に流れる電流の大きさ
は、入力電圧E1，E2の電位差に比例するため、
帰還コンデンサ３の電荷の充放電も電位差に比例
する。しかるに、第２図に示す出力電圧E0の電
位の傾きは、E1，E2の電位差に比例して変化す
る。 When formula (1) is expanded, G (s) = 1/sT 1 +T 2 /T 1 ...(2). That is, it has proportional-integral characteristics of integral and proportional. Note that the magnitude of the current flowing through the input resistor 2 is proportional to the potential difference between the input voltages E 1 and E 2 , so
The charging and discharging of the feedback capacitor 3 is also proportional to the potential difference. However, the slope of the potential of the output voltage E 0 shown in FIG. 2 changes in proportion to the potential difference between E 1 and E 2 .

係る比例積分回路を集積回路（ic）化する場合
には、入出力用のピン３個と外付けのCR部品を
必要とし、ic化による外付け部品の削減及びピン
数削減の妨げとなつていた。また、CR部品のバ
ラツキや電源電圧の変化、温度変化、経時変化等
を受け易いものであつた。さらに、モード指令信
号によりその周波数特性を多モードに切換えたい
場合は、より多くの外付け部品を必要とする等々
の問題があつた。 When converting such a proportional-integral circuit into an integrated circuit (IC), three input/output pins and external CR components are required, which hinders the reduction of external components and the number of pins due to IC conversion. Ta. In addition, it was susceptible to variations in CR components, changes in power supply voltage, changes in temperature, changes over time, etc. Furthermore, if it is desired to switch the frequency characteristics to multiple modes using a mode command signal, there are problems such as the need for more external components.

発明の目的 本発明は前記従来の問題点を解消するもので、
全ての構成要素をデイジタル化し、かつモード指
令信号による周波数特性の切換えを可能にしたデ
イジタル式比例積分回路を提供するものである。OBJECT OF THE INVENTION The present invention solves the above-mentioned conventional problems.
The present invention provides a digital proportional-integral circuit in which all components are digitalized and frequency characteristics can be switched by a mode command signal.

発明の構成 本発明は、モード指令信号によりクロツクパル
スの分周比を切換える可変分周手段と、入力デイ
ジタル信号が所定値のときに前記可変分周手段の
出力を禁止するゲート手段と、前記入力デイジタ
ル信号の最上位の少なくとも１ビツトをアツプダ
ウン信号入力とし、前記ゲート手段の出力をクロ
ツク入力とするアツプダウンカウンタと、前記入
力デイジタル信号に係数を乗じる乗算手段と、前
記アツプダウンカウンタの出力と前記乗算手段の
出力とを加算または減算する加算または減算手段
とを具備し、前記加算または減算手段より出力デ
イジタル信号を得るデイジタル式比例積分回路で
あり、全ての構成要素をデイジタル化すると共に
モード指令信号により低周波領域のゲイン、即ち
周波数特性を切換え可能としたものである。ま
た、本発明は前記ゲート手段の代わりに比例分周
手段を用いる構成とし、前記比例分周手段におい
て前記可変分周手段の出力を入力デイジタル信号
と所定値との差の絶対値に比列した周波数に分周
する構成とし、この出力をアツプダウンカウンタ
のクロツクとして用いれば、比例積分回路の性能
を高めることができる。Structure of the Invention The present invention comprises: variable frequency dividing means for switching the frequency division ratio of clock pulses in response to a mode command signal; gate means for inhibiting the output of said variable frequency dividing means when an input digital signal is a predetermined value; an up-down counter that uses at least one most significant bit of a signal as an up-down signal input and the output of the gate means as a clock input; multiplication means that multiplies the input digital signal by a coefficient; and an output of the up-down counter and the multiplication device. This digital proportional-integral circuit is provided with an addition or subtraction means for adding or subtracting the output from the output of the means, and obtains an output digital signal from the addition or subtraction means. It is possible to switch the gain in the low frequency region, that is, the frequency characteristics. Further, the present invention is configured to use proportional frequency dividing means in place of the gate means, and in the proportional frequency dividing means, the output of the variable frequency dividing means is proportional to the absolute value of the difference between the input digital signal and a predetermined value. The performance of the proportional-integral circuit can be improved by configuring the frequency to be divided into frequencies and using this output as the clock for the up-down counter.

実施例の説明 第３図は本発明の一実施例を示すブロツク図で
あり、第４図はその動作波形図、第５図は比例積
分特性を示す周波数特性曲線である。DESCRIPTION OF THE EMBODIMENTS FIG. 3 is a block diagram showing an embodiment of the present invention, FIG. 4 is its operating waveform diagram, and FIG. 5 is a frequency characteristic curve showing proportional-integral characteristics.

第３図において、５は可変分周手段、６はゲー
ト手段、７はアツプダウンカウンタ、８は乗算手
段、９は加算手段であり、D1は２進数の入力デ
イジタル信号、D2はアツプダウンカウンタの出
力、D3は乗算手段の出力、D4は出力デイジタル
信号、S1はクロツクパルス、S2は可変分周手段の
出力、S3はゲート出段の出力である。 In FIG. 3, 5 is a variable frequency dividing means, 6 is a gate means, 7 is an up-down counter, 8 is a multiplication means, 9 is an addition means, D1 is a binary input digital signal, and D2 is an up-down counter. The output of the counter, D3 is the output of the multiplication means, D4 is the output digital signal, S1 is the clock pulse, S2 is the output of the variable frequency dividing means, and S3 is the output of the gate output stage.

クロツクパルスS1は可変分周手段５においてモ
ード指令信号に応じた所定の分周比で分周され、
その分周出力S2をゲート手段６の入力とする。ゲ
ート手段６では入力デイジタル信号D1が所定値
D0と一致（D1＝D0）とき分周出力S2を禁止し、
不一致（D1≠D0）のとき分周出力S2をゲート出
力S3とし、アツプダウンカウンタ７のクロツク入
力とする。一方、アツプダウンカウンタ７には入
力デイジタル信号D1の最上位の少なくとも１ビ
ツトをアツプダウン信号として入力し、ゲート出
力S3をアツプまたはダウンカウントする。そし
て、アツプダウンカウンタ７より積分された出力
信号D2を得る。また、入力デイジタル信号D1は
乗算手段８に入力し、係数Ｋを乗じる。そして、
加算手段９においてアツプダウンカウンタ７の出
力D2と乗算手段８の出力D3とを加算し、加算出
力D4を出力デイジタル信号として得る構成にし
ている。 The clock pulse S1 is frequency-divided by the variable frequency dividing means 5 at a predetermined frequency division ratio according to the mode command signal.
The frequency-divided output S2 is input to the gate means 6. In the gate means 6, the input digital signal D1 is set to a predetermined value.
When D 0 matches (D 1 = D 0 ), the divided output S 2 is prohibited,
When there is a mismatch (D 1 ≠D 0 ), the divided output S 2 is used as the gate output S 3 and is used as the clock input of the up-down counter 7. On the other hand, at least one most significant bit of the input digital signal D1 is input to the up-down counter 7 as an up-down signal, and the gate output S3 is counted up or down. Then, an integrated output signal D2 is obtained from the up-down counter 7. Further, the input digital signal D1 is input to the multiplication means 8 and multiplied by a coefficient K. and,
The adder 9 adds the output D 2 of the up-down counter 7 and the output D 3 of the multiplier 8 to obtain an added output D 4 as an output digital signal.

第４図により第３図の動作を説明すれば、入力
デイジタル信号D1が所定値D0より大か小かによ
りアツプダウンカウンタ７の動作をアツプかダウ
ン（またはダウンかアツプ）に切換えている。即
ち、出力D2はD1とD0の関係が、D1＞D0（または
D1＜D0）のときアツプカウント（t2〜t3）、D1＝
D0のときカウント停止（t1〜t2、t3〜t4、t5〜）、
D1＜D0（またはD1＞D0）のときダウンカウント
（〜t1、t4〜t5）させる構成にしている。ここで、
D1＞D0かD1＜D0かの検出は、入力デイジタル信
号D1の最上位の少なくとも１ビツトを利用すれ
ばよい。 To explain the operation of FIG. 3 with reference to FIG. 4, the operation of the up/down counter 7 is switched between up and down (or down and up) depending on whether the input digital signal D1 is larger or smaller than a predetermined value D0. . That is, the output D 2 has a relationship between D 1 and D 0 such that D 1 > D 0 (or
When D 1 < D 0 ), up count (t 2 to t 3 ), D 1 =
Counting stops when D 0 (t 1 ~ t 2 , t 3 ~ t 4 , t 5 ~),
It is configured to count down (~ t1 , t4 ~ t5 ) when D1 < D0 (or D1 > D0 ). here,
To detect whether D 1 >D 0 or D 1 <D 0 , it is sufficient to use at least one most significant bit of the input digital signal D 1 .

即ち、入力デイジタル信号D1が６ビツトで、
所定値D0が100000の場合（これは最上位の１ビ
ツトが１で下位ビツトが全て０の場合である）を
例にとり、D1の最上位ビツトが１のときD1＞D0
とし、０のときD1＜D0とすれば簡単に大か小か
の検出が可能である。この場合、所定値D0を
011111としても同様の検出が可能である。 That is, if the input digital signal D1 is 6 bits,
For example, when the predetermined value D 0 is 100000 (this is the case where the most significant bit is 1 and all the lower bits are 0), when the most significant bit of D 1 is 1, D 1 > D 0
If D 1 <D 0 when 0, it is possible to easily detect whether the value is large or small. In this case, the predetermined value D 0 is
Similar detection is also possible with 011111.

上記の例は、所定値D0を入力デイジタル信号
D1の1/2の値に設定する場合であるが、1/4、3/4
の値に設定することも可能であり、この場合は最
上位の２ビツトをアツプダウン信号として用いれ
ばよく、この場合は検出のための論理回路（デコ
ーダ）が必要である。 In the above example, input digital signal with predetermined value D 0
D is set to 1/2 of 1 , but 1/4, 3/4
It is also possible to set the value to . In this case, the most significant two bits may be used as an up-down signal, and in this case, a logic circuit (decoder) for detection is required.

一方、ゲート手段６では入力デイジタル信号
D1をデコードし、D1＝D0のとき禁止信号を得て
分周出力S2のゲート出力禁止を行なう。 On the other hand, in the gate means 6, the input digital signal
D1 is decoded, and when D1 = D0 , a prohibition signal is obtained and gate output of the frequency-divided output S2 is prohibited.

ここで、(2)式の時定数T1は、 T1＝１／CK ……(3) として求めることができる。但し、CKはアツプ
ダウンカウンタ７に入力されるクロツクパルスの
周波数である。このクロツク周波数CKはクロツ
クパルスS1を可変分周手段５でモード指令信号に
応じて分周した分周出力S2のの周波数である。 Here, the time constant T 1 in equation (2) can be obtained as T 1 =1/ CK (3). However, CK is the frequency of the clock pulse input to the up-down counter 7. This clock frequency CK is the frequency of the divided output S2 obtained by dividing the clock pulse S1 by the variable frequency dividing means 5 according to the mode command signal.

可変分周手段５、ゲート手段６、アツプダウン
カウンタ７で成る積分回路の出力D2と、入力デ
イジタル信号D1に係数Ｋを乗じた乗算手段８の
出力D3とを加算手段９において加算すれば、(2)
式の比例要素T2／T1を付加することができる。
即ち、 T2／T1＝Ｋ ……(4) となる。 The output D 2 of the integrating circuit consisting of the variable frequency dividing means 5, the gate means 6, and the up-down counter 7 and the output D 3 of the multiplication means 8, which is the input digital signal D 1 multiplied by the coefficient K, are added in the addition means 9. If (2)
The proportional element T 2 /T 1 of the equation can be added.
That is, T 2 /T 1 =K (4).

以上により比例積分回路を全デイジタル化でき
ると共に可変分周手段５の分周比をモード指令信
号に応じて切換え、分周出力S2の周波数が、1、
2、3…の2π倍となるように分周すれば、第５図
に示すように本発明の目的とする比例積分回路の
低周波領域のゲイン、即ち、周波数特性を切換え
ることができる。 As described above, the proportional integral circuit can be fully digitalized, and the frequency dividing ratio of the variable frequency dividing means 5 can be changed according to the mode command signal, so that the frequency of the frequency divided output S2 is 1 ,
By dividing the frequency by 2π times 2 , 3 , . . . , it is possible to switch the gain in the low frequency region of the proportional-integral circuit, which is the object of the present invention, that is, the frequency characteristics, as shown in FIG.

なお、アツプダウンカウンタ７の動作を、D1
＞D0のときダウンカウント、D1＜D0のときアツ
プカウントする構成とするときは、加算手段９を
減算手段とすることで入力デイジタル信号D1に
対する出力デイジタル信号D4を負極性とするこ
とができる。 Note that the operation of the up-down counter 7 is expressed as D 1
If the configuration is such that a down count is performed when D 0 >D 0 and an up count is performed when D 1 <D 0 , the adding means 9 is used as a subtracting means to make the output digital signal D 4 negative in polarity relative to the input digital signal D 1 . be able to.

次に、第６図は本発明の第２の実施例を示すブ
ロツク図であり、第３図の実施例と異なるのは、
第３図のゲート手段６の代わりに比例分周手段１
０を用いた点である。D0は所定値、S4は比例分
周子段１０の出力である。比例分周手段１０は可
変分周子段５の分周出力S2を受け、入力デイジタ
ル信号D1と所定値D0との差の絶対値に比例した
周波数に分周し、その分周出力S4をアツプダウン
カウンタ７のクロツク入力とする。これにより、
入力デイジタル信号D1と所定値D0との差の絶対
値｜D1−D0｜に比例したアツプカウント、ダウ
ンカウントが可能である。これは、丁度第１図の
従来例で入力の電位差に比例して帰還コンデンサ
の充放電を行なうのをデイジタル的に具現したも
のである。ここで、(3)式のクロツク周波数CKは
比例分周手段１０の出力S4の最低周波数、即ち、
｜D1−D0｜＝１のときの周波数である。 Next, FIG. 6 is a block diagram showing a second embodiment of the present invention, which differs from the embodiment in FIG.
Proportional dividing means 1 instead of gate means 6 in FIG.
This is the point using 0. D 0 is a predetermined value, and S 4 is the output of the proportional frequency divider stage 10. The proportional frequency dividing means 10 receives the frequency divided output S2 of the variable frequency divider stage 5, divides the frequency into a frequency proportional to the absolute value of the difference between the input digital signal D1 and the predetermined value D0 , and outputs the frequency divided output S2. 4 is the clock input of the up-down counter 7. This results in
Up-counting and down-counting are possible in proportion to the absolute value |D 1 -D 0 | of the difference between the input digital signal D 1 and the predetermined value D 0 . This is a digital implementation of the conventional example shown in FIG. 1 in which the feedback capacitor is charged and discharged in proportion to the input potential difference. Here, the clock frequency CK in equation (3) is the lowest frequency of the output S4 of the proportional frequency dividing means 10, that is,
This is the frequency when |D 1 −D 0 |=1.

以上説明した第１、第２実施例のアツプダウン
カウンタ７には、計数出力D2をデコードしてD2
が最大値及び最小値のときに入力されるクロツク
S3，S4の入力を禁止すると共に最大値を検出した
ときは次のダウン指令で、最小値を検出したとき
は次のアツプ指令でクロツク入力禁止を解除する
機能を付加する。これにより、アツプダウンカウ
ンタ７のオーバーフロー及びアンダーフローを防
止できる。 The up-down counter 7 of the first and second embodiments described above decodes the count output D 2 and outputs D 2
Clock input when is maximum and minimum value
A function is added that prohibits the input of S 3 and S 4 and cancels the inhibition of clock input with the next down command when the maximum value is detected, and with the next up command when the minimum value is detected. Thereby, overflow and underflow of the up-down counter 7 can be prevented.

また、必要な複数のクロツクパルスが用意され
ている場合は、可変分周手段５の代わりにモード
指令信号によるクロツク選択手段を用いても差し
使えないことは言うまでもない。 It goes without saying that if a plurality of necessary clock pulses are prepared, a clock selection means based on a mode command signal may be used instead of the variable frequency dividing means 5.

発明の効果 以上の説明で明らかな如く、全ての構成要素を
デイジタル化し、モード指令信号に応じて比例積
分回路の低周波領域のゲイン、即ち周波数特性を
切換えることができ、かつic化に好適で、その実
用的効果は大である。Effects of the Invention As is clear from the above explanation, all the components are digitalized, and the gain in the low frequency region of the proportional-integral circuit, that is, the frequency characteristic, can be switched according to the mode command signal, and it is suitable for IC implementation. , its practical effects are great.

【図面の簡単な説明】[Brief explanation of drawings]

第１図はアナログ式比例積分回路の従来構成を
示す電気的線図、第２図はその動作波形図、第３
図は本発明のデイジタル式比例積分回路の１実施
例のブロツク図、第４図はその動作波形図、第５
図はその周波数特性曲線図、第６図は本発明の他
の実施例のブロツク図である。 ５……可変分周手段、６……ゲート手段、７…
…アツプダウンカウンタ、８……乗算手段、９…
…加算または減算手段、１０……比例分周手段。 Figure 1 is an electrical diagram showing the conventional configuration of an analog proportional-integral circuit, Figure 2 is its operating waveform diagram, and Figure 3 is an electrical diagram showing the conventional configuration of an analog proportional-integral circuit.
The figure is a block diagram of one embodiment of the digital proportional-integral circuit of the present invention, FIG. 4 is its operating waveform diagram, and FIG.
The figure is a frequency characteristic curve diagram thereof, and FIG. 6 is a block diagram of another embodiment of the present invention. 5... variable frequency dividing means, 6... gate means, 7...
...Up-down counter, 8...Multiplication means, 9...
...addition or subtraction means, 10...proportional frequency division means.

Claims (1)

【特許請求の範囲】 １ モード指令信号によりクロツクパルスの分周
比を切換える可変分周手段と、入力デイジタル信
号が所定値のときに前記可変分周手段の出力を禁
止するゲート手段と、前記入力デイジタル信号の
最上位の少なくとも１ビツトをアツプダウン信号
入力とし、前記ゲート手段の出力をクロツク入力
とするアツプダウンカウンタと、前記入力デイジ
タル信号に係数を乗じる乗算手段と、前記アツプ
ダウンカウンタの出力と前記乗算手段の出力とを
加算または減算する加算または減算手段とを具備
し、前記加算または減算手段よりモード指令信号
に対応した出力デイジタル信号を得ることを特徴
とするデイジタル式比例積分回路。 ２ モード指令信号によりクロツクパルスの分周
比を切換える可変分周手段と、前記可変分周手段
の出力を入力デイジタル信号と所定値との差の絶
対値に比例した周波数に分周する比例分周手段
と、前記入力デイジタル信号の最上位の少なくと
も１ビツトをアツプダウン信号入力とし、前記第
２分周手段の出力をクロツク入力とするアツプダ
ウンカウンタと、前記入力デイジタル信号に係数
を乗じる乗算手段と、前記アツプダウンカウンタ
の出力と前記乗算手段の出力とを加算または減算
する加算または減算手段とを具備し、前記加算ま
たは減算手段よりモード指令信号に対応した出力
デイジタル信号を得ることを特徴とするデイジタ
ル式比例積分回路。[Scope of Claims] 1. Variable frequency dividing means for switching the frequency division ratio of the clock pulse in response to a mode command signal, gate means for inhibiting the output of the variable frequency dividing means when the input digital signal is a predetermined value, and an up-down counter that uses at least one most significant bit of a signal as an up-down signal input and the output of the gate means as a clock input; multiplication means that multiplies the input digital signal by a coefficient; and an output of the up-down counter and the multiplication device. 1. A digital proportional-integral circuit comprising: an addition or subtraction means for adding or subtracting an output from the output means; and an output digital signal corresponding to a mode command signal is obtained from the addition or subtraction means. 2. variable frequency dividing means for switching the frequency division ratio of the clock pulse according to a mode command signal; and proportional frequency dividing means for dividing the output of the variable frequency dividing means into a frequency proportional to the absolute value of the difference between the input digital signal and a predetermined value. an up-down counter that uses at least one most significant bit of the input digital signal as an up-down signal input and an output of the second frequency dividing means as a clock input; and a multiplication means that multiplies the input digital signal by a coefficient; A digital type, comprising an addition or subtraction means for adding or subtracting the output of the up-down counter and the output of the multiplication means, and obtaining an output digital signal corresponding to the mode command signal from the addition or subtraction means. Proportional-integral circuit.
JP59071977A 1984-04-11 1984-04-11 Digital type proportion integration circuit Granted JPS60215242A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59071977A JPS60215242A (en) 1984-04-11 1984-04-11 Digital type proportion integration circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59071977A JPS60215242A (en) 1984-04-11 1984-04-11 Digital type proportion integration circuit

Publications (2)

Publication Number Publication Date
JPS60215242A JPS60215242A (en) 1985-10-28
JPH0241768B2 true JPH0241768B2 (en) 1990-09-19

Family

ID=13476026

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59071977A Granted JPS60215242A (en) 1984-04-11 1984-04-11 Digital type proportion integration circuit

Country Status (1)

Country Link
JP (1) JPS60215242A (en)

Also Published As

Publication number Publication date
JPS60215242A (en) 1985-10-28

Similar Documents

Publication Publication Date Title
US6177787B1 (en) Circuits and methods for controlling timing and slope compensation in switching regulators
US5594631A (en) Digital pulse width modulator for power supply control
US8030976B2 (en) Triangle wave generating circuit
US20180191356A1 (en) Control circuit
US9306543B2 (en) Temperature-compensated high accuracy clock
US10833654B2 (en) Oscillator circuit with comparator delay cancelation
JP2509426B2 (en) Delta-Sigma-Analog / Digital Converter
JPH0241768B2 (en)
JP5589769B2 (en) Switching power supply control circuit and electronic device
JPH0241766B2 (en)
JPH0241767B2 (en)
JPH06244639A (en) Frequency synthesizer
JPH0142434B2 (en)
CN109407744B (en) Linear constant current control system and method for constant current control of a load
JPH0465569B2 (en)
Panetas-Felouris et al. Digital to Pulse-Width Converter for Time-Mode PWM signal processing
JPH08111641A (en) Comparison device, A / D conversion device, PWM signal generation device, power supply device, power supply control device
JP5527397B1 (en) Pulse generator
US11456747B1 (en) Multiphase frequency to voltage converter
JP2519545Y2 (en) Cascade integration type A / D converter
SU718918A1 (en) Digital follow-up decade
JPH05243857A (en) Offset immune type switched capacitor amplifier circuit
JP3424198B2 (en) Direct digital synthesizer
KR940008192B1 (en) Frequency divider with 50 percentage duty
TWI496074B (en) Multiplier-divider and method thereof