JPH024190B2 - - Google Patents
Info
- Publication number
- JPH024190B2 JPH024190B2 JP57148908A JP14890882A JPH024190B2 JP H024190 B2 JPH024190 B2 JP H024190B2 JP 57148908 A JP57148908 A JP 57148908A JP 14890882 A JP14890882 A JP 14890882A JP H024190 B2 JPH024190 B2 JP H024190B2
- Authority
- JP
- Japan
- Prior art keywords
- information
- processor
- busy
- communication path
- section
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/167—Interprocessor communication using a common memory, e.g. mailbox
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Multi Processors (AREA)
- Information Transfer Systems (AREA)
- Exchange Systems With Centralized Control (AREA)
- Small-Scale Networks (AREA)
Description
【発明の詳細な説明】
(a) 発明の技術分野
本発明はプロセツサ間データ通信方式、特に第
一のプロセツサの保持する内線話中情報（以下、
単に情報という）を受信して所定の処理を実行す
る複数の第二のプロセツサを具備するマルチプロ
セツサシステムにおけるプロセツサ間データ通信
方式に関す。DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to an inter-processor data communication system, and in particular to an extension busy information (hereinafter referred to as
The present invention relates to an inter-processor data communication method in a multiprocessor system including a plurality of second processors that receive information (simply referred to as information) and execute predetermined processing.
(b) 従来技術と問題点
第１図はこの種マルチプロセツサシステムにお
ける従来あるプロセツサ間データ通信方式の一例
を示す図である。第１図において、第二のプロセ
ツサとしてのｎ個の情報受信側プロセツサ１（以
後個々の情報受信側プロセツサ１を示す場合、１
−１乃至１−ｎと称す）と、第一のプロセツサと
しての１個の情報送信側プロセツサ２とが、情報
通信路３を介して結合されている。情報送信側プ
ロセツサ２は、例えば構内交換機における総ての
内線の話中情報の如き、共通の情報を情報蓄積部
８に保持している。各情報受信側プロセツサ１
は、例えば中継台に指定された百番代の内線群の
話中状態を表示する如き前記情報を用いる処理を
実行する処理部４を内蔵する。情報受信側プロセ
ツサ１−１において、処理部４が特定百番代内線
群の話中表示処理を実行する場合には、情報要求
部５を起動し、情報通信路３を介して情報送信側
プロセツサ２に所要百番代を示す情報要求信号を
伝達する。該情報要求信号を受信した情報送信側
プロセツサ２は、要求識別部６により要求元情報
受信側プロセツサ１および要求する百番代を識別
し、情報編集部７に通知する。情報編集部７は該
当百番代の内線話中情報を情報蓄積部８から抽出
し、要求元情報受信側プロセツサ１−１の識別情
報を宛先情報として付加し、所定の情報形式に編
集した後情報通信路３に送出する。各情報受信側
プロセツサ１の情報識別部９は、情報通信路３か
ら到着する情報に付加されている宛先情報を分析
し、自己宛の情報と識別すると、該情報を情報受
信部１０を介して処理部４に伝達する。所要の情
報を受信した処理部４は、所要百番代の内線の話
中状態を中継台に表示する等の、所要の処理を実
行する。(b) Prior Art and Problems FIG. 1 is a diagram showing an example of a conventional inter-processor data communication system in this type of multiprocessor system. In FIG. 1, there are n information receiving processors 1 (hereinafter, when individual information receiving processors 1 are indicated, 1
-1 to 1-n) and one information transmitting processor 2 serving as a first processor are coupled via an information communication path 3. The information transmitting processor 2 stores common information in an information storage section 8, such as busy information for all extensions in a private branch exchange. Each information receiving processor 1
has a built-in processing section 4 that executes processing using the information, such as displaying the busy status of the 100th extension group designated as the relay console. In the information receiving processor 1-1, when the processing unit 4 executes busy display processing for a specific 100-digit extension group, it starts the information requesting unit 5 and sends the information to the information transmitting processor via the information communication path 3. 2, an information request signal indicating the required number of 100 numbers is transmitted. The information transmitting processor 2 that has received the information request signal uses the request identifying section 6 to identify the requesting information receiving processor 1 and the requested 100 number, and notifies the information editing section 7 of the same. The information editing section 7 extracts the extension busy information of the corresponding 100th number from the information storage section 8, adds the identification information of the request source information receiving processor 1-1 as destination information, and edits it into a predetermined information format. It is sent to the information communication channel 3. The information identification unit 9 of each information receiving processor 1 analyzes the destination information added to the information arriving from the information communication channel 3, and when it identifies the information as addressed to itself, the information is sent via the information receiving unit 10. The information is transmitted to the processing unit 4. The processing unit 4 that has received the required information executes necessary processing, such as displaying the busy status of the required 100th extension on the relay stand.
以上の説明から明らかな如く、従来あるプロセ
ツサ間データ通信方式においては、内線話中情報
を必要とする各情報受信側プロセツサ１は、情報
通信路３を介して情報送信側プロセツサ２に情報
要求信号を伝達せねばならぬ為、情報要求部５を
設ける必要が有り、また情報送信側プロセツサ２
は、情報要求信号を分析する要求識別部６を設
け、該情報要求信号を受信する度に所要百番代の
内線話中情報を送出する必要が有る。また各情報
受信側プロセツサ１からの情報要求信号が集中し
て発生した場合には、情報受信側プロセツサ１は
過負荷状態となる。特に複数の情報受信側プロセ
ツサ１から同一百番代の内線話中情報を要求され
た場合にも、情報送信側プロセツサ２は該同一情
報を総ての要求元情報受信側プロセツサ１に対し
繰返し伝達する必要が有り、効率の悪い情報通信
を実行することとなり、当該マルチプロセツサシ
ステムの処理効率の低下を招く恐れが有る。 As is clear from the above explanation, in the conventional inter-processor data communication system, each information receiving processor 1 that requires extension busy information sends an information request signal to the information transmitting processor 2 via the information communication path 3. must be transmitted, it is necessary to provide an information request section 5, and the information transmitting processor
It is necessary to provide a request identification section 6 that analyzes the information request signal, and to send out extension busy information for the required 100 numbers each time the information request signal is received. Further, when information request signals from each information receiving processor 1 are generated in a concentrated manner, the information receiving processor 1 becomes overloaded. In particular, even when multiple information receiving processors 1 request extension busy information for the same number, the information transmitting processor 2 repeats the same information to all the requesting information receiving processors 1. This results in inefficient information communication, which may lead to a decrease in the processing efficiency of the multiprocessor system.
(c) 発明の目的
本発明の目的は、前述の如き従来あるプロセツ
サ間データ通信方式の欠点を除去し、情報通信の
際の、情報送信側および情報受信側プロセツサの
負荷を極力減少させ、効率の良いプロセツサ間デ
ータ通信方式を実現することに在る。(c) Purpose of the Invention The purpose of the present invention is to eliminate the drawbacks of the conventional inter-processor data communication system as described above, to reduce the load on the information transmitting side and information receiving side processors as much as possible during information communication, and to improve efficiency. The objective is to realize a good inter-processor data communication system.
(d) 発明の構成
この目的は、交換機に収容されるすべての内線
の話中情報を保持する第一のプロセツサと、中継
台等に内蔵され、中継台より指定される内線群の
話中状態を表示するための処理機構を有する複数
の第二のプロセツサとの間で、前記第一のプロセ
ツサから第二のプロセツサへ前記話中情報を伝達
するマルチプロセツサシステムにおいて、前記第
一のプロセツサと前記第二のプロセツサとの間に
特定の情報通信路を設け、前記第一のプロセツサ
は該情報通信路に前記保持する情報を所定周期で
順次送出し、前記各第二のプロセツサは前記情報
通信路から順次伝達される情報から前記中継台よ
り指定された内線群の話中情報のみを抽出するこ
とにより達成される。(d) Structure of the Invention The purpose of this invention is to provide a first processor that maintains busy information of all extensions accommodated in an exchange, and a processor that is built into a relay console and stores busy status information of a group of extensions designated by the relay console. In the multiprocessor system, the busy information is transmitted from the first processor to the second processor between the first processor and a plurality of second processors each having a processing mechanism for displaying the busy information. A specific information communication path is provided between the first processor and the second processor, the first processor sequentially sends the held information to the information communication path at a predetermined period, and each of the second processors transmits the information communication path to the information communication path. This is achieved by extracting only the busy information of the designated extension group from the relay stand from the information sequentially transmitted from the relay.
(e) 発明の実施例
以下、本発明の一実施例を図面により説明す
る。第２図は本発明の一実施例によるプロセツサ
間データ通信方式を示す図である。なお、全図を
通じて同一符号は同一対象物を示す。第２図にお
いては、ｎ個の情報受信側プロセツサ１と情報送
信側プロセツサ２との間に、内線話中情報伝達用
の情報通信路３′が専用に設けられている。情報
送信側プロセツサ２の情報編集部７は、情報蓄積
部８が保持する内線話中情報を各百番代分宛所定
周期で順次抽出し、百番代識別情報を付加して所
定の情報形式に編集した後、情報通信路３′に順
次送出する。各情報受信側プロセツサ１におい
て、特定百番代内線群の話中表示処理を実行する
処理部４は、所要百番代を示す情報要求信号をを
情報識別部９に伝達する。該情報識別部９は、情
報通信路３′から周期的に到着する情報の具備す
る百番代識別情報を分析し、処理部４から受信し
ている情報要求信号の示す百番代と一致した情報
を抽出し、情報受信部１０を介して処理部４に伝
達する。該情報を受信した処理部４は、前記所要
の処理を実行する。(e) Embodiment of the invention An embodiment of the invention will be described below with reference to the drawings. FIG. 2 is a diagram showing an inter-processor data communication system according to an embodiment of the present invention. Note that the same reference numerals indicate the same objects throughout the figures. In FIG. 2, an information communication path 3' for transmitting information during an extension call is provided exclusively between n information receiving processors 1 and information transmitting processors 2. The information editing section 7 of the information transmitting processor 2 sequentially extracts the extension busy information held by the information storage section 8 for each 100th generation at a predetermined period, adds 100th generation identification information, and converts it into a predetermined information format. After editing the data, the data is sequentially sent to the information communication channel 3'. In each information receiving processor 1, a processing section 4 that executes a busy display process for a specific 100's extension group transmits an information request signal indicating the required 100's to the information identifying section 9. The information identification unit 9 analyzes the 100-digit identification information included in the information periodically arriving from the information communication path 3', and determines whether it matches the 100-digit identification information indicated by the information request signal received from the processing unit 4. Information is extracted and transmitted to the processing unit 4 via the information receiving unit 10. The processing unit 4 that has received the information executes the required processing.
以上の説明から明らかな如く、本実施例によれ
ば、各情報受信側プロセツサ１は情報要求信号を
情報送信側プロセツサ２に伝達する必要が無い為
情報要求部５を設ける必要が無く、また情報送信
側プロセツサ２は情報受信側プロセツサ１からの
情報要求信号を受信分析する必要が無い為要求識
別部６を設ける必要が無く、更に情報送信側プロ
セツサ２は所定周期で内線話中情報を順次送出す
る為、負荷が平均化され過負荷となる恐れは無
い。また同一百番代の内線話中情報を繰返し送出
する無効通信は避けられる。 As is clear from the above description, according to this embodiment, each information receiving processor 1 does not need to transmit an information request signal to the information transmitting processor 2, so there is no need to provide the information requesting section 5, and Since the transmitting processor 2 does not need to receive and analyze the information request signal from the information receiving processor 1, there is no need to provide a request identification section 6, and furthermore, the information transmitting processor 2 sequentially sends extension busy information at a predetermined period. Therefore, the load is averaged and there is no risk of overload. In addition, invalid communication in which the extension busy information of the same 100th number is repeatedly sent can be avoided.
なお、第２図はあく迄本発明の一実施例に過ぎ
ず、例えば情報受信側プロセツサ１は中継台に所
要百番代の内線話中状態を表示する処理に限定さ
れることは無く、他に幾多の変形が考慮される
が、何れの場合にも本発明の効果は変らない。更
に情報受信側プロセツサ１および情報送信側プロ
セツサ２の構成、並びに情報通信路３′の形態は
図示されるものに限定されることは無く、他に幾
多の変形が考慮されるが、何れの場合にも本発明
の効果は変らない。 It should be noted that FIG. 2 is merely one embodiment of the present invention, and for example, the information receiving processor 1 is not limited to the process of displaying the busy status of the required 100th extension on the relay stand, and may also be used for other purposes. Although many modifications may be considered, the effects of the present invention remain the same in any case. Furthermore, the configurations of the information receiving processor 1 and the information transmitting processor 2 and the form of the information communication path 3' are not limited to those shown in the drawings, and many other modifications may be considered; However, the effect of the present invention remains unchanged.
(f) 発明の効果
以上、本発明によれば、前記マルチプロセツサ
システムにおいて、第一および第二のプロセツサ
の間の情報通信に要する負荷を軽減するプロセツ
サ間データ通信方式が実現可能となり、当該マル
チプロセツサシステムの処理能力が向上する。(f) Effects of the Invention As described above, according to the present invention, it is possible to realize an inter-processor data communication method that reduces the load required for information communication between the first and second processors in the multiprocessor system. The processing power of multiprocessor systems is improved.
第１図は従来あるプロセツサ間データ通信方式
の一例を示す図、第２図は本発明の一実施例によ
るプロセツサ間データ通信方式を示す図である。
図において、１は情報受信側プロセツサ、２は
情報送信側プロセツサ、３および３′は情報通信
路、４は処理部、５は情報要求部、６は要求識別
部、７は情報編集部、８は情報蓄積部、９は情報
識別部、１０は情報受信部１０、を示す。
FIG. 1 is a diagram showing an example of a conventional inter-processor data communication system, and FIG. 2 is a diagram showing an inter-processor data communication system according to an embodiment of the present invention. In the figure, 1 is an information receiving processor, 2 is an information transmitting processor, 3 and 3' are information communication channels, 4 is a processing section, 5 is an information request section, 6 is a request identification section, 7 is an information editing section, and 8 9 indicates an information storage section, 9 indicates an information identification section, and 10 indicates an information reception section 10.
Claims (1)
を保持する第一のプロセツサと、中継台等に内蔵
され、中継台より指定される内線群の話中状態を
表示するための処理機構を有する複数の第二のプ
ロセツサとの間で、前記第一のプロセツサから第
二のプロセツサへ前記話中情報を伝達するマルチ
プロセツサシステムにおいて、前記第一のプロセ
ツサと前記第二のプロセツサとの間に特定の情報
通信路を設け、前記第一のプロセツサは該情報通
信路に前記保持する情報を所定周期で順次送出
し、前記各第二のプロセツサは前記情報通信路か
ら順次伝達される情報から前記中継台より指定さ
れた内線群の話中情報のみを抽出することを特徴
とするプロセツサ間データ通信方式。1. A first processor that holds busy information for all extensions accommodated in the exchange, and a processing mechanism that is built into a relay stand, etc. and that displays the busy status of a group of extensions specified by the relay stand. In a multiprocessor system that transmits the busy information from the first processor to the second processor between the first processor and the second processor, A specific information communication path is provided, the first processor sequentially sends the held information to the information communication path at a predetermined period, and each second processor extracts the information from the information sequentially transmitted from the information communication path. An inter-processor data communication method characterized by extracting only busy information for a designated group of extensions from a relay stand.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14890882A JPS5938871A (en) | 1982-08-27 | 1982-08-27 | Inter-processor data communicating system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14890882A JPS5938871A (en) | 1982-08-27 | 1982-08-27 | Inter-processor data communicating system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5938871A JPS5938871A (en) | 1984-03-02 |
| JPH024190B2 true JPH024190B2 (en) | 1990-01-26 |
Family
ID=15463345
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14890882A Granted JPS5938871A (en) | 1982-08-27 | 1982-08-27 | Inter-processor data communicating system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5938871A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0834616B2 (en) * | 1987-04-20 | 1996-03-29 | 富士通株式会社 | Synchronization method of common data in multi-processor system |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS537267B2 (en) * | 1973-06-28 | 1978-03-16 |
-
1982
- 1982-08-27 JP JP14890882A patent/JPS5938871A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5938871A (en) | 1984-03-02 |
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