JPH0241929B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a data holding circuit constituting a data processing device, and in particular to a synchronous flip-flop, which is capable of independently controlling a plurality of latches constituting the flip-flop. This makes it possible to hold multiple different pieces of data as needed.

BACKGROUND OF THE INVENTION Conventionally, in data processing devices, logic circuits are often constructed using master-slave or D-type flip-flops as data holding circuits.

Figures 1 and 2 show general circuit configuration examples of master-slave and D-type flip-flops, respectively. It can be seen as consisting of a synchronizing latch or a group of latches provided at the front stage for holding data at the timing, and a latch for final data holding provided at the rear stage. Once the synchronization latches at the front stage perform a timing operation and transfer the held data to the latch at the rear stage, they are not used until the next data input operation, and are no longer functional. is in a dormant state.

For example, the period during which such a data holding circuit holds one piece of data varies depending on the purpose of use, but it can be as short as several clocks, or as long as several minutes to several hours, such as when displaying a mode. In any case, the hardware utilization efficiency of the synchronization latch at the preceding stage can be seen to be extremely low.

By the way, the scale of a data processing device integrated into an IC is determined by the number of basic gates that can be mounted on the IC, so gates with poor utilization efficiency, such as some of the latches that make up the flip-flop mentioned above, are
This is one of the major factors that limits the performance of data processing devices that can be realized, and in other words, it is an obstacle to miniaturization and lower power consumption of the devices.

OBJECT AND CONFIGURATION OF THE INVENTION An object of the present invention is to enable a plurality of latches that are constituent elements of a data holding circuit used in a data processing device to be used independently, and to The object of the present invention is to provide a data processing device that can utilize basic gates with high efficiency by using latches that are available to hold data that has different purposes and times of use.

The present invention has a configuration for this purpose, which includes a first latch and a second latch, and a first latch at the leading edge of a data input and one clock input.
In a single-bit data retention circuit, the first latch and the second latch hold the data; a switch means provided at a connecting portion of the second latch for switching connection and disconnection between the latches, a signal input means for controlling the switch means, and an output connection to the second latch being disconnected by the switch means; and an output signal take-out means provided at the output part of the first latch, and after the data of the first latch is held by the second latch, the switching means connects the first latch and the second latch. cut the bond between the first
The latch is characterized in that it can be used as a separate data holding circuit and can be used to hold different data.

Embodiments of the Invention The present invention will be described below with reference to Examples.

FIG. 3 shows an embodiment circuit in which the present invention is applied to a master-slave flip-flop. In the figure, 1 is an inverter, 2 and 3 are 2-input AND gates, 4 is a 2-input NOR gate, 5 is an inverter, 6 and 7 are 3-input NAND gates,
8 and 9 indicate two-input NAND gates.

The overall circuit configuration is similar to that shown in FIG. 1, with elements 1-5 forming the first latch and elements 6-8 forming the second latch. In addition,
Q _M and _M represent the outputs of the first latch, and Q _S and _S represent the outputs of the second latch. The circuit of this embodiment differs from the conventional circuit in that a separation control signal S is applied to the logic inputs of the NAND gates 6 and 7.

During the period in which the separation control signal S takes a value of "1", the entirety functions as one edge trigger type flip-flop.

FIG. 4 shows operating waveforms in this case.
Input data is read into the second latch at the leading edge of the clock and holds the data until the next clock input, as shown by the waveform at point A. For the first latch, the clock is OFF.
When this happens, the data in the first latch is taken in by NAND gates 6 and 7, and the data is held thereafter.

Next, when the separation control signal S shows a value of “0”, the outputs of the NAND gates 6 and 7 are always “1”.
, the first latch is logically separated from the first latch and continues to retain its previous data.

FIG. 5 shows the equivalent circuit of the first latch in the above example. As can be seen, input data is read into the latch synchronously with the clock. Therefore, while S = "0", the first latch can function as an independent clock-synchronized latch using the output terminals Q _M and _M without affecting the second latch. . In this embodiment, the reset input is omitted for the sake of simplicity.

FIG. 6 shows an embodiment in which the present invention is applied to a D-type flip-flop. In the figure, 10 is a latch, and 11 is a second latch portion, which corresponds to the conventional circuit shown in FIG.
In this embodiment, two NAND gates 12 and 13 are inserted between the two latches as isolation gates and are controlled by isolation control signal S in the same manner as in FIG. In this case, when the clock is on, the logical values of Q _M and _M are “1”.
Therefore, it has no meaning, but data can be retained in other states.

[Brief explanation of drawings]

1 and 2 are circuit diagrams showing configuration examples of conventional synchronous flip-flops, FIG. 3 is a circuit diagram of a synchronous flip-flop according to an embodiment of the present invention, and FIG. An operating waveform diagram when the control signal S is set to "1"; FIG. 5 is an equivalent circuit diagram of the first latch when the separation control signal S is set to "0" in the circuit of FIG. 3;
FIG. 6 is a circuit diagram of a D type flip-flop according to an embodiment of the present invention. In the figure, 1 is a NAND gate, 2 and 3 are AND gates
Gate, 4 is NOR gate, 5 is inverter, 6
9 to 9 are NAND gates, and are different latch stages, Q _M and _M are the outputs of the first latch, Q _S
and _S represents the second latch stage, and S represents the isolation control signal.

Claims (1)

Claims: 1. Consisting of a first latch and a second latch, the first latch holds data at the leading edge of a data input and one clock input, and the second latch holds data at the trailing edge of said clock input. In a single-bit data holding circuit that holds data held in the first latch, the latch is provided at a joint between the first latch and the second latch to connect and disconnect the latch. a switch means for switching the latch; a signal input means for controlling the switch means; and an output signal take-out means provided at the output part of the first latch whose output connection to the second latch is cut by the switch means. After the data of the first latch is held by the second latch, the switching means breaks the connection between the first latch and the second latch, and
A data holding circuit characterized in that the latch can be used as a separate data holding circuit and can be used to hold different data.