JPS59220A - Data holding circuit - Google Patents

Abstract

PURPOSE:To raise the utilization efficiency of a fundamental gate, and to hold different data, by constituting a titled circuit so that plural latches cab be used independently, and using the latch ready to use among said latches, for holding the data whose use purposes and use time are different. CONSTITUTION:A latch stage I of prestage is constituted of an NAND gate 1, AND gates 2, 3, an NOR gate 4 and an invertor 5, and a latch stage II of poststage is constituted of NAND gates 6-9, which become master and slave FF circuits. The timing operation is executed by the latch stage I of this prestage, and holding data is transferred to the latch stage II of poststage. A split controlling signal S is inputted to a logical input of the NAND gates 6, 7 of this circuit, the input data is read into the latch stage I by the leading edge of a clock, is held until the following clock input, and when the clock is off, the data is inputted by the latch stage II of poststage by the NAND gates 6, 7, and different data is held by separating logically the latch stages I , II.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a data holding circuit constituting a data processing device, and particularly to a synchronous flip-flop, which is capable of independently controlling a plurality of launches constituting the flip-flop. The KI is designed so that it can hold multiple different pieces of data as needed.

BACKGROUND OF THE INVENTION Conventionally, in data processing devices, logic circuits are often constructed using master-slave or D-type flip-flops as data holding circuits.

Figures 1 and 2 show general circuit configuration examples of master-slave and D-type flip-flops, respectively.As is clear from Figure 9, these flip-flops do not clock input data. It can be seen as consisting of a synchronization latch or a group of latches provided in the first stage (Il) for holding data at a specific timing, and a final data holding latch provided in the second stage. Once these pre-stage synchronization switches perform a timing operation and transfer the held data to the post-stage latch, they are not used until the ninth data input operation is performed.

It is functionally dormant.

For example, the period during which such a data holding circuit holds one piece of data varies depending on the purpose of use, but it can be as short as several clocks, or as long as the mode display. In any case, what is the hardware usage efficiency of the synchronization latch in the previous stage?

Normally, it can be seen as being in a very low state.

By the way, the scale of data processing equipment converted to IC is
Because it is determined by the basic number of gates that can be installed in the device, some gates that are inefficient in their use, such as some of the latches that make up the flip-flops mentioned above.

This is one of the major factors that limits the performance of data processing devices that can be realized, and in other words, it is an obstacle to miniaturization and lower power consumption of the devices.

An object of the present invention is to provide a data holding circuit for use in a data processing device as a component thereof.

By making multiple latches available for use independently, and by using the available latches to hold data with different purposes and times, the efficiency of basic gate usage can be improved. Our goal is to provide high quality data processing equipment.

To achieve this, the present invention provides a single-bit data holding circuit that is configured with a plurality of latches and operates synchronously based on data input and one clock input, in which a single-bit data holding circuit is provided at the coupling portion of each latch. , a switch means for switching connection and disconnection between latches, a signal input means for controlling the switch means, and an output signal output provided at the output part of the latch whose output connection to other latches is cut by the switch means. The present invention is characterized in that it has a means for cutting the coupling between each latch as necessary to enable each latch to be used as a separate data holding circuit.

The present invention will be explained below based on two examples.

FIG. 3 shows an embodiment circuit in which the present invention is applied to two master-slave lip-flop circuits. In the same figure, 1
is an inverter, 2 and 3 digit 2-man power AND gate, 4 digit 2-man power NOR gate, 5 digit inverter, 6 and 7 are 3
Human powered NAND gate.

8 and 9 indicate two-man powered NAND gates.

The overall circuit configuration is the same as that shown in FIG. 1, with elements 1 to 5 as the first latch, and elements 6 to 8 as
It forms a latch. In addition.

QM, QM represents the output of the first latch t Qs* Q8 represents the output of the second latch. The circuit of this embodiment differs from the conventional circuit in that the 9-minute female control signal S is applied to the logic input of the NAND gate 6.7.

During the period in which the separation control signal S takes a value of 1'', the entire circuit functions as one edge-trigger type flip-flop.

FIG. 4 shows operating waveforms in this case.

The input data is the leading edge of the clock.
The data is read into the second latch, and the data is held until the ninth clock input, as shown by the waveform at point A. The second latch takes in the data of the first latch through the NAND gates 6 and 7 when the clock reaches 0FFK, and thereafter holds the data.

Next, when the 9-separation control signal S shows a value of "0",
The output of the NAND gate 6.7 is always 1'', and the second latch is logically separated from the first latch and continues to hold the previous data.

FIG. 5 shows the isochoric circuit of the second latch in the above example. As is clear from the figure, input data is read into the latch in synchronization with the clock. Therefore, 3=
During "0", the first latch can function as a latch synchronized with an independent clock using the output terminals QM and QM without affecting the second latch. In addition.

In this embodiment, the reset input is omitted for simplicity.

FIG. 6 shows an embodiment in which the present invention is applied to a D-type flip-flop. In the figure, numeral 10 is a first latch, and 11 is a latch part 2, which corresponds to the conventional circuit shown in FIG.

In this embodiment, two NAND gates 12 and 13 are inserted between the two latches as isolation gates, and are controlled by the isolation control signal S in the same manner as in FIG. In this case, when the clock is ON, +
Since the logical value of QM+QM is "1", it has no meaning, but data can be held in other states.

[Brief explanation of the drawing]

1 and 2 are circuit diagrams showing configuration examples of conventional synchronous flip-flops, FIG. 3 is a circuit diagram of a synchronous flip-flop according to an embodiment of the present invention, and FIG. 4 is a circuit diagram of a synchronous flip-flop according to an embodiment of the present invention. 5 is an equivalent circuit diagram of the first latch when the 9-separation control signal Sf is set to "O" in the circuit of FIG. 3;
FIG. 6 is a circuit diagram of a D type flip-flop according to an embodiment of the present invention. In the figure, 1 digit NAND gate, 2i- and 3 are AND
Gate, 4 is NOR gate, 5 is inverter, 6 to 9
is a NAND gate, ■ and ■ are different latch stages, Q
M and 4M represent the outputs of the first latch, Qs and Q8 represent the second latch stage, and S represents the separation control signal. Patent applicant Fujitsu Ltd. Representative Patent Attorney Fumihiro Hase (1 other person) 10

Claims (1)

[Scope of Claims] In a single-bit data holding circuit that is constituted by a plurality of latches and operates synchronously using a data gate and one clock circuit, a single-bit data holding circuit is provided at a coupling portion of each latch,
: Switch means for switching connection and disconnection between the 7 latches, signal input means for controlling the switch means, and an output provided at the exit portion of the latch whose output connection to other latches is cut by the switch means. A signal extraction means is provided. A data retention circuit characterized in that the coupling between each latch is cut as necessary to enable each latch to be used as a separate data retention circuit.