JPH0242437B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION This invention is used in an echo detection device that emits waves such as radio waves and sound waves through a rotating directional beam and receives the reflected waves as a detection signal. The present invention relates to an echo detection display device that converts the detection signal into a detection signal and displays it on a horizontal and vertical scanning type display.

<Prior art> In conventional radar, the detection direction θ and detection distance l are converted into orthogonal coordinates l _cps θ, l _sio θ by coordinate transformation,
A memory is addressed using the converted coordinates to store the detection signal, and the memory is read out and displayed on the display in synchronization with the scanning of the horizontal/vertical scanning display. In this case, the memory is provided with memory cells corresponding to each pixel of the display screen of the horizontal/vertical scanning display, as shown in FIG. 1, for example. When a reflected signal is obtained from the detection distance l ₁ in the detection direction θ ₁ , a high level 1 is written in the memory cell M ₁₁ addressed by l _1cps θ ₁ and l _1sio θ ₁ . Furthermore, when a reflected signal is obtained at a detection direction θ ₂ and a detection distance l ₂ that are close to this, 1 is written in the memory cell M ₂₂ designated by l _2cps θ ₂ and l _2sio θ ₂ .
The detection signal thus written is read out and displayed on the display in synchronization with the scanning of the display.

When the radar detection range is changed, for example from a short detection range to a long range,
The detection area corresponding to one memory cell becomes wider. For example, in a short detection range, the detection direction θ ₁ and the detection distance l ₁ and the detection direction θ ₂ and the detection distance l ₂ each correspond to one memory cell, When the range is increased, the detection distance for one memory cell M ₁₁ is around l 1 and the detection direction _{θ 1 as} shown in the enlarged view in
All reflected signals between θ ₄ and θ 4 are matched. Therefore, as shown in this example, in the detection directions θ ₁ , θ ₂ , and θ ₃ , reflected signals were obtained at the detection distance l ₁ , but in the detection direction θ ₄ , the reflected waves were obtained at the detection distance l ₁ . If not, θ ₁ θ ₂ …
When sequential detection scanning is performed, 0 is written in the memory cell _M11 , indicating that there is no reflected wave.
In other words, in the detection direction θ ₁ to θ ₃ , the memory cell
Data 1 indicating that there is a reflected wave is written to _M11 , but 0 is written to the memory cell _M11 indicating that there is no reflected wave at the detection distance _l1 of the detection direction _θ4 .

For this reason, although reflective objects are displayed when the detection range is set to a short range, when the detection range is switched to a long detection range, the display of the previously displayed reflective objects may disappear. In this way, when the same area is being detected, it is undesirable for the display to appear and disappear when the range is changed.

<Summary of the Invention> The present invention provides an echo detection display device that can always display reflected signals regardless of switching of detection ranges.

According to this invention, two memories for storing detection signals are provided, and these memories are alternately switched such that one is used for writing and the other is used for erasing every detection scan, and the detection signal is kept at a predetermined level. Only in the above case, data is written to the memory currently designated for writing, and when the level is below a predetermined level, data indicating zero or no reflection is not written to the memory designated for writing. In other words, only data indicating that there is a reflection is written. On the other hand, the memory designated for erasing is addressed by the converted coordinates of the same coordinate converting means at that time, and data indicating that there is no reflection is written to that part, that is, erased. These memories are always read out simultaneously and in synchronization with the scanning of the display and provided to the display as a display signal. By doing this, when data for multiple directions and multiple unit detection distances are shared for one memory cell of the memory, and if a reflection is obtained for any one of them, that memory cell is The fact that a reflection was obtained is memorized. Therefore, even if the detection range is changed, there is no fear that the display of the reflected wave at the same location will disappear or appear, and if there is a reflection, the display of the reflecting object will always be obtained at the corresponding position.

<Embodiment> FIG. 3 shows a case where an example of the echo detection display device of the present invention is applied to a radar. radar antenna 1
1, the control and transmitting/receiving unit 12 rotates the pointing direction of the antenna beam, and a signal indicating its reference direction, or the heading direction if this radar is installed on a ship, for example, is obtained at the terminal 13, and furthermore, the direction of the directed beam is turned. A signal indicating the current azimuth, that is, the detection direction θ, is output to terminal 14, a signal indicating the transmission timing is output to terminal 15, and a reference clock indicating that the radio wave has advanced by a unit distance after the transmission timing is output to terminal 16. be done. Also, the reflected wave is received, amplified and detected, and its output, that is, the detection signal, is sent to the terminal 17.
The signal is supplied to the AD converter 18 from

In this example, in the AD converter 18, depending on whether the detection signal is above or below a predetermined level, it is determined that there is a reflected wave or there is no reflected wave, and the reflected wave is output. This conversion in AD converter 18 is performed in synchronization with the clock at terminal 16. Reference direction signal of terminal 13, terminal 1
The detection direction signal at terminal 4, the transmission timing signal at terminal 15, and the reference clock at terminal 16 are input to the write control section 19. The writing converter 19 converts the polar coordinates into orthogonal coordinates l _cps θ and l _sio θ in correspondence with the detection direction θ and the detection distance l based on these input signals, and the x coordinate value is set to the terminal 21.
The x and y coordinate values are output to the terminal 21y, and a write pulse is output to the terminal 22.

The horizontal/vertical scanning display 23 is similar to a so-called television receiver, and its display surface is main scanned horizontally or vertically, and separate vertically or horizontally, and each scan is synchronized with the scanning. The position is indicated by orthogonal coordinates, the x coordinate is output to the terminal 24x, and the y coordinate is output to the terminal 24y, and the display signal input to the terminal 25 is displayed at the position on the screen specified by the x and y coordinates. Display modulation.

In this invention, two memories 26 and 27 are provided, and these memories 26 and 27 are connected to the display 23.
The read data is logically summed through the OR circuit 28 and sent to the terminal 25 of the display 23 as a display signal.
is supplied to In this example, the display data is binary data, and the output of the OR circuit 28 is supplied as is to the display 23. However, if the read data is multi-valued, it is converted to analog data and then sent to the display 23. If the display 23 is a color signal, the read data is converted into a color signal corresponding to its level (magnitude) and supplied to the display 23.

The memories 26 and 27 are alternately switched between writing and erasing for each detection scan of the radar. The address specified by the output of the write converter 19 is specified for the one for writing.
The detection signal from the AD converter 18 is written, and in that case, only those above a predetermined level are written. Further, the address of the memory designated for erasing is specified by the write converter 19 and that portion is erased, that is, the same operation is performed when a conventional write indicating that there is no reflected signal is performed.

That is, the output of the AD converter 18 is switched to the selector switch 3.
1 and 32, and the switching outputs of the changeover switches 31 and 32 are input to the write data input terminals D of the memories 26 and 27, respectively. Changeover switch 3
1 and 32 are switched inversely to each other, and the changeover switch 3
1 is connected to the AD converter 18 on the a side, the selector switch 32 is connected on the b side to the AD converter 18, and the selector switch 31 is connected on the b side.
The a side of the changeover switch 32 is grounded.
Further, the output sides of these switches 31 and 32 are connected to one input side of OR circuits 33 and 34, and the other input sides of OR circuits 33 and 34 are connected to the output sides of changeover switches 35 and 36, respectively. The changeover switches 35 and 36 are also switched in opposite directions, and the a side of the changeover switch 35 and the b side of the changeover switch 36 are grounded, respectively.The b side of the changeover switch 35 and the a side of the changeover switch 36 are connected to the terminals. 37, and its terminal 37 is given a high level. The output side of OR circuits 33 and 34 is
connected to one input side of the AND circuits 38 and 39;
A write pulse from the terminal 22 of the write converter 19 is applied to the other input sides of the AND circuits 38 and 39, respectively. Also, AND circuits 38, 39
The memories 26 and 27 are write-controlled by the output.

The converted coordinate signal output from the write converter 19 is supplied to address switching circuits 41, 42 through terminals 21x, 21y, and these address switching circuits 41, 42 are supplied to terminals 24x, 24y.
Coordinate signals indicating the scanning position of the display 23 are inputted from each of the display units 23 and 23. A switching signal is sent from the terminal 43 from this write converter 19 to the address switching circuit 4.
1 and 42, and during each memory cycle of the memories 26 and 27, the coordinate signals from the write converter 19 and the coordinate signals from the display 23 are alternately switched and given as addresses to the memories 26 and 27, respectively. It will be done. That is, during one half of each memory cycle, the memories 26 and 27 are in a write state, and the other half are in a read state. Also, terminal 13
The azimuth reference signal is supplied to the switching control circuit 44,
The changeover switches 31, 32, 35, and 36 are controlled in conjunction with the output of the changeover control circuit 44. All these switches are simultaneously switched to side a or side b for each detection scan. The changeover switches 31, 32, 35, and 36 are usually configured electronically.

For example, as shown in the figure, selector switches 31, 3
2, 35, and 36 are connected to the a side, the output of the AD converter 18 is supplied to the memory 26, and the memory 26 is used for writing, and the zero level from the changeover switch 32 is input to the write data of the memory 27. The memory 27 is supplied to the terminal for erasing. Also, at this time, the output of the switch 35 receives zero level from the a side, so the AD
AND circuit 38 only when it is determined that the output from converter 18 is at a predetermined level, that is, there is a reflected signal.
A high level is applied to the terminal 21, and the write pulse generated at that time causes its reflected signal to
It is addressed and written into the memory 26 by the x, 21y coordinates.

On the other hand, for the memory 27, a higher level than that from the terminal 37 is always applied to the AND circuit 39 through the switch 36, so that the write pulse is applied to the terminal 27.
2, the terminals 21x and 21y at that time
A zero is written by the switch 32 to the portion specified by the address, that is, that portion is erased. When one writing detection scan is completed, all addresses for the memories 26 and 27 are specified, so that all the memory cells of the memory 27 are in an erased state at this time. During each generation of this write pulse, the memories 26 and 27 are addressed and read out simultaneously by the coordinate signals from the terminals 24x and 24y, and the readout output is supplied as a display signal to the display 23, and its contents are is displayed.

Therefore, even in the state shown in FIG. 2, for example, the reflected signal at the distance l ₁ in the azimuths θ ₁ , θ ₂ , and θ ₃ is written in the memory cell M ₁₁ of the memory 26, and the reflected signal at the distance l ₁ in the azimuth θ ₄ is written. There is no reflected signal, but at this time the output of the selector switch 31 is at a low level and the OR
Since the output of the circuit 33 is at a low level, the write pulse at the terminal 22 cannot pass through the AND circuit 38, and writing to the memory 26 is not performed. Therefore, in the memory cell _M11 , if even one of the four data is reflected, data indicating that there is a reflection is written, and there is no possibility that this data will be erased. Therefore, even if the detection range is changed, if even one reflection is obtained in that memory cell, this will be stored and there is no fear that the display will disappear when the detection range is changed.

In this way, since no-reflection data is not written to memory cells corresponding to areas where there is no reflection, past reflection data will remain written unless switches 31, 32, 35, and 36 are switched. As a result, each address in the memory 26 is in a reflected state. However, one memory 27 is erased, and the erasure and writing are alternately switched for each detection scan, so past data does not remain for a long time, and the memory 27 is based on new detection signals for each scan. Writing is performed. That is, in this example, when the next detection scan starts, a reference direction pulse is generated at the terminal 13, and the switching control circuit 44 switches the switches 31 and 3.
2, 35, and 36 are all switched to the b side, and the memory 26 is given a zero level to the data input terminal D by the switch 31 for erasing, and the memory 27
The output of the AD converter 18 is applied to the data input terminal D by the switch 32 for writing. Writing to the memory 27 is performed only when a high level is obtained from the AD converter 18, but the memory 26 is always connected to the terminal 3 of the OR circuit 33.
A level higher than 7 is always applied, and each memory cell will be completely erased after one detection scan.

Note that if the speeds of the memories 26 and 27 are slow, the data are converted and written in parallel. Further, the present invention can be applied not only to radar but also to sonar and other echo detection devices.

<Effects> As described above, according to the echo detection display device of the present invention, two memories are provided, one for writing and the other for erasing, which are switched every detection scan, and both are read at the same time. Therefore, regardless of the switching of the detection range, if there is a reflective object, the reflective object can always be displayed at the corresponding position.

[Brief explanation of the drawing]

Figure 1 shows the relationship between memory storage status, detection direction, and detection distance. Figure 2 shows an example where multiple pieces of detection data are shared with one memory cell when the detection lens becomes larger. FIG. 3 is a block diagram showing an example of an echo detection display device according to the present invention. 12: Control transmitter, 18: AD converter, 19:
Writing converter, 21x, 21y: Conversion coordinate output terminal, 23: Display device, 24x, 24y: Display device scanning position coordinate output terminal, 26, 27: Memory, 4
1, 42: Address switching circuit.

Claims (1)

[Claims] 1 Coordinate conversion means for converting the detection direction and detection distance into orthogonal coordinates, a horizontal/vertical scanning display, and a display that is simultaneously read out in synchronization with the scanning of the display, and synthesizes the read output to display the display on the display. a first and a second memory which supply a display signal to the first and second memories;
a switching means for alternately switching one of the second memories for writing and the other for erasing every detection scan;
A detection signal of a predetermined level or higher is addressed by the coordinates converted by the coordinate conversion means according to the detection direction and detection distance, and the first and second
a writing means that writes to a memory that is intended for writing and does not write to a detected signal below the predetermined level; and a coordinate conversion means that writes to a memory that is intended for erasing in the first and second memories. and erasing means for addressing and erasing by the transformed coordinates of the echodetector display device.