JPH0242507A - Program control device - Google Patents

Abstract

PURPOSE:To easily produce and maintain a program including the signal state changed by the lapse of time when such a program is required by storing the signal states of the desired frequency covering the past through the future and easily referring to the contents of storage of said signal states. CONSTITUTION:A processor 1 which performs the overall control includes an index 2 and a mask register 3. An input circuit 13 receives an external signal and transmits this signal to a bus 12 after converting the signal level. Then an output circuit 14 outputs an output signal to the outside from the inside. Only in case an input signal I1 is presently kept on and also was kept on in the preceding scan cycle I1-1 and its preceding scan period I1-2 respectively, an output signal Q1 is turned on. In other words, a function is secured as a kind of a filter that turns on the output only when the ON states are continuous in three times. Thus a program can be produced and maintained in consideration of the lapse of time.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a PC (programmable controller) device, and particularly to a PC device that operates in a cyclic scan method.

[Conventional technology]

A conventional cyclic scan type PC device has an internal memory that corresponds to external input/output signals on a one-to-one basis, and reads the state of the external signal into the internal memory at each scan cycle. After performing calculations on the data, the external signals were updated according to the calculation results left in the internal memory.

[Problem to be solved by the invention]

In conventional PC devices, there was only one set of internal memories for storing signal states. Therefore, if you try to create a program that is aware of changes in signal states over time, such as determining the current output based on the signal states of both the current scan period and the previous scan period, the scan The program had to be especially conscious of processing such as storing the signal state for each cycle in another internal memory for the next calculation. As a result, the program becomes complicated, which is disadvantageous in terms of program creation and maintenance.

The present invention has been made in view of these points, and it is an object of the present invention to provide a PC device in which logic including the passage of time can be easily programmed.

[Means to solve the problem]

In order to solve the above-mentioned problems, the present invention provides a PC device using a cyclic scan method. There is provided a PC device, characterized in that signal states of scan cycles of are both stored in a memory, and the contents stored in the memory can be individually referenced from a user program.

[Operation] A mask register and an index register are prepared inside the processor, and the number of times a signal should be stored is set in the mask register. Also, the index register is 0
It is automatically added for each scan to indicate the range from to the value set in the mask register.

When interpreting the address part specified in the instruction of the user program, the effective address, that is, the address to be actually referenced, is determined by calculations between the address part, the mask register, and the index register.

〔Example〕

Hereinafter, one embodiment of the present invention will be described based on the drawings.

FIG. 1 shows a block diagram of the hardware of a PC according to the present invention. In the figure, 1 is a processor for overall control, and includes an index register 2 (hereinafter referred to as IR) and a mask register 3 (hereinafter referred to as MR). 4 is a ROM, which stores a system program 5 and the like. A RAM 6 stores a user program 7, an input signal memory 8, an output signal memory 9, and the like.

10 is a programmer interface, which connects the programmer 11 and the lotus 12. An input circuit 13 receives a signal from the outside, converts the signal level, and transmits it to the path 12. 14 is an output circuit, which outputs an output signal from the inside to the outside.

FIG. 2 is a time chart showing the operation results of an example of the program. As shown in the figure, in this example, the human input signal ■
1 is currently ON and the previous scan cycle (11
-1) and the scan cycle #J4 (11-2) before the previous time, the output signal Ql is turned ON only when it is ON. That is, it operates as a type of filter that turns on the output only when the ON state continues three times.

FIG. 3 is an example of a program in which the functions of the above-mentioned filter are displayed in monic language.

This program includes each step shown in Figure 4.

is converted into a 16-bit instruction code. Here, the upper two bits (bits 14 and 15) of the instruction code indicate the type of instruction, and the next one bit (pin 13) indicates whether the reference signal is input or output. The remaining 13 bits of the address field (AR) indicate the signal address. The lower 2 bits (bit 0) of the address part (AR) corresponding to MR
．． 1) indicates which scan period from the past to the present the signal is, and the remaining 11 bits (bits 2 to 12)
) indicates the signal number.

FIG. 5 is a diagram showing the configuration of MR and IR, and IR is 0.
1 is added for each scan so as to periodically indicate the range from MR to the value indicated by MR. That is, I.R.
changes to 0O101, 10, 11, and after 11 is OO
Return to

FIGS. 6(a), (b), (c) and (d) are explanatory diagrams of state changes of the input signal memory (IM).

As the IR changes periodically, the correspondence between the signal address referenced in the instruction and the effective address on the input signal memory changes sequentially from FIG. 6(a) to FIG. 6(d). ,
After FIG. 6(d), the process returns to FIG. 6(a).

FIG. 7 is a diagram showing an effective address calculation method.

In this example, by the procedure shown in the figure, IR, MR, and AR
5 is found as the effective address from .

The processor refers to (5) of the input signal memory ([M), and since the IR is 10, as is clear from FIG. 6, the state of input 11 (11-
1) is used for calculation.

In this embodiment, a single memory area is divided into four sections, and in addition to the signal states in the current scan cycle, the signal states in the previous three scan cycles are stored. The contents can be referenced individually from the user program.

In this embodiment, the binary numbers 00.01.10.11 of the lower two bits of the address field (AR) are set to 0 and -, respectively.
I interpreted it as a negative number like 3, -2, -1, so
The signal state of the past scan cycle is now referred to.

However, if these binary numbers are interpreted as positive numbers such as 0, +1, +2, +3, it is possible to indicate the signal state for several scans in the future.

This is effective for programming the output results during future scans, such as capturing the rising edge of a signal and turning on other signals in the next scan.

Furthermore, the above binary numbers 0O101, 10, 11 are changed to 0, +1
, -2, -1, and can also be referred to as the signal state of the scan period from the time before the previous time to the next time.

In addition, the number of MR bits in this embodiment was 2, but as the number of MR bits setting 1 increases to 1, 2, 3, etc., the number of times the signal state can be stored increases from 2 to 4. times, 8 times, etc., and can be set to the required number of times.

Moreover, the PC device of the present invention provides O
By setting , it is possible to operate in the same way as a conventional PC device.

〔Effect of the invention〕

As explained above, in the present invention, the signal state is stored as many times as necessary from the past to the future, and the stored contents are configured to be easily referenced. If a program is needed, it becomes easier to create and maintain the program.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the hardware of a PC device according to an embodiment of the present invention, FIG. 2 is a time chart of an example of a program, FIG. 3 is a diagram showing an example of a program, and FIG. 4 is a diagram of an example of a program. Figure 5 shows the structure of the mask register (MR) and index register (IR). Figure 6 (a), (b), (c) and (d) shows the instruction code of the program example. FIG. 7 is a diagram showing changes in the state of the input signal memory (IM), and FIG. 7 is a diagram showing an effective address calculation method. Processor index register (IR) - Mask register (MR) - ROM - System program - RAM - User program - Input signal memory (IM) - Output signal memory - Programmer interface - Programmer -・Nomas・−Input circuit 2−−−−・・−−−1−・3−・・・・− 4−−−−−1・5−−−−・・ 6−−−−−・7・・−−−〜・・・ 8・−−−−・−−−−・ 9−−−・−・−・ 10−・・・ 11−−−−・−−−−・ 12−・−・ 13 −・・−・ ・・・−Output circuit

Claims (2)

[Claims] (1) In a cyclic scan type PC device, in addition to the signal state in the current scan cycle, the signal state in a predetermined number of scan cycles in both the past scan cycle and the future scan cycle, or both A PC device characterized in that the content is stored in a memory, and the content stored in the memory can be individually referenced from a user program. (2) The first aspect of the present invention is characterized in that the memory is used by dividing a single memory area into a number of sections corresponding to the number of scan cycles in which signal states are to be stored.
PC device described in section.