JPH0242741A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0242741A JPH0242741A JP19311288A JP19311288A JPH0242741A JP H0242741 A JPH0242741 A JP H0242741A JP 19311288 A JP19311288 A JP 19311288A JP 19311288 A JP19311288 A JP 19311288A JP H0242741 A JPH0242741 A JP H0242741A
- Authority
- JP
- Japan
- Prior art keywords
- vernier
- main
- scale
- scales
- field oxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 7
- 238000000034 method Methods 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 238000006073 displacement reaction Methods 0.000 abstract 2
- 238000004519 manufacturing process Methods 0.000 description 4
- 239000003795 chemical substances by application Substances 0.000 description 1
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特にバーニヤパターンを有
する半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device having a vernier pattern.
従来のバーニヤパターンは、同一の下地工程で形成され
た主尺のＸ方向とＸ方向パターンに主尺とは異なる下地
工程で副尺を形成していた。従来例について第２図を参
照りで説明する。（第２図（ａ）、 （ｂ）中の斜線部
は下地工程の違いを示すために便宜的に施したものであ
った断面を示すものではない。）
第２図（ａ）に示すように基板上にフィールド酸化膜１
ａ、ｌｂとゲート電極配線２ａ、２ｂが直交スる下地パ
ターンにフンタクト３を形成する場合について述べる。In a conventional vernier pattern, a vernier scale is formed in the X direction and X direction patterns of the main scale in a base process different from that of the main scale, which are formed in the same base process. A conventional example will be explained with reference to FIG. (The shaded areas in Figures 2(a) and (b) do not represent the cross-sections, which were added for convenience to show the difference in the base process.) As shown in Figure 2(a), field oxide film 1 on the substrate
A case will be described in which the contact 3 is formed on a base pattern in which a, lb and gate electrode wirings 2a, 2b are orthogonal to each other.
第２図（ａ）、 （ｂ）に示すように基板上にフィール
ド酸化膜１ａ、ｌｂを形成した後、７バーニヤのＸ方向
主尺５ａ’〜５ｅ’ とＸ方向主尺４ａ’〜４ｅ’が同
一のゲート電極配線２ａ、２ｂの製造工程で形成されて
おり、この主尺上にフンタクト３の製造工程で形成され
る副尺６＆′〜６ｅ’および７ａ’〜７ｅ’が形成され
る。As shown in FIGS. 2(a) and 2(b), after forming the field oxide films 1a and 1b on the substrate, the X-direction main scales 5a' to 5e' and the X-direction main scales 4a' to 4e' of the seven verniers are formed. are formed in the same manufacturing process for gate electrode wirings 2a and 2b, and vernier scales 6&' to 6e' and 7a' to 7e', which are formed in the manufacturing process of the main unit 3, are formed on this main scale.
上述した従来のバーニヤパターンは主尺のＸ方向とＸ方
向が同一の下地工程で形成されていた。The conventional vernier pattern described above is formed in the same base step in the X direction and the X direction of the main scale.
そのためフィールド酸化膜とゲート電極配線のそれぞれ
の下地工程における目ズレによりコンタクトとフィール
ド酸化膜の目ズレが存在していても、バーニヤパターン
の主尺と副尺との間には目ズレは存在せず、よってフィ
ールド酸化膜のコンタクトに対する目ズレは検出するこ
とができないという欠点を有していた。Therefore, even if there is misalignment between the contact and the field oxide film due to misalignment in the underlying process of the field oxide film and gate electrode wiring, there is no misalignment between the main and vernier dimensions of the vernier pattern. Therefore, it has the disadvantage that misalignment of the field oxide film with respect to the contact cannot be detected.
本発明の半導体装置は、基板上に形成するバーニヤパタ
ーンにおいて、Ｘ方向のバーニヤパターンの主尺とＸ方
向のバーニヤパターンの主尺とがそれぞれ異なる工程で
形成され、かつ、バーニヤパターンの主尺上に配置され
る副尺のＸ方向及びＸ方向は、主尺を形成する工程に対
してさらに異なる一工程で同時に形成され、Ｘ方向、Ｘ
方向が異なる工程で形成された主尺に対する副尺の偏位
の検出が可能なバーニヤパターンを有する。In the semiconductor device of the present invention, in the vernier pattern formed on the substrate, the main scale of the vernier pattern in the X direction and the main scale of the vernier pattern in the X direction are formed in different processes, and the main scale of the vernier pattern is The X direction and the X direction of the vernier scale placed in the
It has a vernier pattern that can detect the deviation of the vernier scale with respect to the main scale formed in processes in different directions.
このような本発明によれば、Ｘ、Ｘ方向の主尺はそれぞ
れ別工程、すなわち、それぞれ別のパターンと整合して
形成されるため、これら各パターンの偏位の検出を確実
に行なうことができる。According to the present invention, since the main scales in the X and X directions are formed in separate processes, that is, in alignment with different patterns, it is possible to reliably detect the deviation of each of these patterns. can.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例の平面図である。FIG. 1 is a plan view of one embodiment of the present invention.
（第１図（ａ）、 （ｂ）中の斜線部は、下地工程の違
いを示すものであって、断面を示すものではない。）第
１図（ａ）に示すようなフィールド酸化膜１ａ。(The shaded areas in FIGS. 1(a) and (b) indicate the difference in the underlying process and do not indicate the cross section.) Field oxide film 1a as shown in FIG. 1(a) .
１ｂとゲート電極配線２ａ、２ｂが直交する下地パター
ンにコンタクト３を形成する場合について述べる。第１
図（ａ）、 （ｂ）に示すようにバーニヤのＸ方向主尺
５ａ〜５ｅは、ゲート電極配線２ａ。A case will be described in which the contact 3 is formed on a base pattern in which the gate electrode wirings 1b and the gate electrode wirings 2a and 2b are perpendicular to each other. 1st
As shown in FIGS. (a) and (b), the main lengths 5a to 5e of the vernier in the X direction are gate electrode wiring 2a.
２ｂの製造工程で形成され、Ｘ方向主尺４ａ〜４ｅは、
フィールド酸化膜１ａ、ｌｂの製造工程で形成され、副
尺６ａ〜６ｅおよび７ａ〜７ｃは、コンタクト３の製造
工程で形成される。したがって主尺５ａ〜５ｅは配線２
ａ、２ｂと自己整合関係を有し、主尺６ａ〜６ｅはフィ
ールド酸化膜１ａ。2b, and the main scales 4a to 4e in the X direction are
The field oxide films 1a and 1b are formed in the manufacturing process, and the vernier scales 6a to 6e and 7a to 7c are formed in the contact 3 manufacturing process. Therefore, the main scales 5a to 5e are the wiring 2
a, 2b, and main scales 6a to 6e are field oxide films 1a.
１ｂのバタンと自己整合関係を有している。It has a self-aligning relationship with the button 1b.
すなわち、本発明のバーニヤパターンは、基板上にフィ
ールド酸化膜１ａ、ｌｂを形成する際に同時にＸ方向主
尺４ａ〜４ｅを形成し、その後、ゲート電極２ａ、２ｂ
を形成する際に同時にＸ方向主尺５ａ〜５ｅを形成し、
コンタクト３を形成する際に同時に副尺６ａ〜Ｂｅ、７
ａ〜７ｃを形成する。このように形成されたバーニヤパ
ターンは、下地に対する目ズレをＸ方向、Ｘ方向とも各
工程間で厳密にチエツクが可能となる。That is, in the vernier pattern of the present invention, when forming the field oxide films 1a and lb on the substrate, the main scales 4a to 4e in the X direction are simultaneously formed, and then the gate electrodes 2a and 2b are formed.
When forming the main scales 5a to 5e in the X direction at the same time,
At the same time when forming the contact 3, the vernier scales 6a to Be, 7
Form a to 7c. With the vernier pattern formed in this way, it is possible to precisely check the misalignment with respect to the base between each process in both the X direction and the X direction.
以上説明したように本発明のバーニヤパターンは、主尺
のＸ方向とＸ方向がそれぞれ異なる下地工程によって形
成され、この主尺に対し、さらに異なる下地工程により
副尺な形成することによって、下地との相対目ズレをＸ
方向、Ｘ方向に独立して厳密に判定できる効果がある。As explained above, the vernier pattern of the present invention is formed in the X direction and the The relative misalignment of
This has the effect of making it possible to accurately determine the direction and the X direction independently.
ニヤパターン、第２図（ａ）は従来の能動素子領域の平
面図、第２図（ｂ）は従来のバーニヤパターンである。FIG. 2(a) is a plan view of a conventional active element area, and FIG. 2(b) is a conventional vernier pattern.
ｌａ、ｌｂ・・・・・・フィールド酸化膜、２ａ、２ｂ
・・・・・・ゲート電極配線、３・・団・コンタクト％
４＆〜４ ｅ、４ａ’ 〜４ ｅ’−Ｘ方向主尺、５ａ
〜５ｅ、５ａ 〜５ｅ ・・・・・・Ｘ方向主尺％
６ａ〜６ｅ、６ａ’〜６ｅ ・・・・・・Ｘ方向副尺、
７ａ〜７ｅ、７ａ 〜７ｅ’・・・・・・Ｘ方向副尺
。la, lb...field oxide film, 2a, 2b
・・・・・・Gate electrode wiring, 3・Group・Contact%
4 & ~4 e, 4a' ~4 e'-X direction main scale, 5a
~5e, 5a ~5e...X direction main scale%
6a to 6e, 6a' to 6e...X direction vernier scale,
7a to 7e, 7a to 7e'... X direction vernier scale.
代理人 弁理士 内 原 晋Agent Patent Attorney Susumu Uchihara
第１図（ａ）は、本発明の半導体装置における能動素子
領域の平面図、第１図（ｂ）は本発明のバ−６．２」（
圏−４ａ
６ｂ−’叱に４ｂ
６ｃノテ＋４Ｃ
（ａ）
図
６４ノもト克
６４ジニΔ＝５５≧５ａｂ’
（ａ）
（ｂン
第Ｚ図FIG. 1(a) is a plan view of the active element region in the semiconductor device of the present invention, and FIG. 1(b) is the bar 6.2 of the present invention.
Circle-4a 6b-' 4b 6c Note + 4C (a) Figure 64 Nomo Tokke 64 Gini Δ=55≧5ab' (a)
Claims (1)
方向の前記バーニヤパターンの第１の主尺と、該第１の
主尺とは異なる工程で形成されたＹ方向の前記バーニヤ
パターンの第２の主尺と、前記第１および第２の主尺上
に配置され、前記バーニヤパターンの主尺を形成する工
程とは異なる工程で形成されるＸ方向およびＹ方向の前
記バーニヤパターンの副尺とを有することを特徴とする
半導体装置。In a vernier pattern formed on a semiconductor substrate,
a first main scale of the vernier pattern in the direction, a second main scale of the vernier pattern in the Y direction formed in a different process from the first main scale, and the first and second main scales. A semiconductor device comprising: a vernier scale of the vernier pattern in the X direction and the Y direction, which is disposed above the vernier pattern and formed in a process different from a process of forming the main scale of the vernier pattern.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19311288A JPH0242741A (en) | 1988-08-01 | 1988-08-01 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19311288A JPH0242741A (en) | 1988-08-01 | 1988-08-01 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0242741A true JPH0242741A (en) | 1990-02-13 |
Family
ID=16302451
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19311288A Pending JPH0242741A (en) | 1988-08-01 | 1988-08-01 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0242741A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04186672A (en) * | 1990-11-16 | 1992-07-03 | Nec Ic Microcomput Syst Ltd | Master-slice integrated circuit |
| JPH0917714A (en) * | 1995-06-29 | 1997-01-17 | Nec Corp | Alignment method and alignment error inspection method |
-
1988
- 1988-08-01 JP JP19311288A patent/JPH0242741A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04186672A (en) * | 1990-11-16 | 1992-07-03 | Nec Ic Microcomput Syst Ltd | Master-slice integrated circuit |
| JPH0917714A (en) * | 1995-06-29 | 1997-01-17 | Nec Corp | Alignment method and alignment error inspection method |
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